By Jonathan Davis, president, SEMI Global Semiconductor Business
The transition to manufacturing semiconductors on larger wafers continues to be one of the hottest topics in the industry. Some chipmakers have committed to advancing the transition. Intel announced that its D1X fab in Oregon will be 450mm compatible (2013). TSMC announced a 450mm pilot line by 2013-2014. IMEC and ISMI have well-established programs focused on the challenges posed by manufacturing with 450mm wafers and the University of Albany's College of Nanoscale Science and Engineering (CNSE) is expanding facilities to encompass 450 program R&D.
With increasing interest in a near-term 450mm pilot line development, many critical elements need coordination for affordable high-volume 450 manufacturing to occur. At the recent SEMICON West 450 Wafer Transition Forum, panelists from throughout the supply chain grappled with the numerous issues involved. Uncertainty with EUV rollout has exacerbated the 450mm planning challenge and is reinforcing the need for more transparency in planning and funding.
Thomas Sonderman, VP of Manufacturing Technology at GLOBALFOUNDRIES, summarized well the need to clarify time tables and trigger points during his presentation at West, saying “We’re getting to the point where it costs more and more money to make these transitions and there’s a real need to make sure that when we do it, we do it right as an industry.” He continued, “Clearly there is a value to doing this; the challenge is going to be ‘how do you do it, what’s the mechanism to drive collaboration?’ A few companies will get together work together and synergize as a fab community so that we’re working with the supplier community to make sure we’re all in synch as we go down this path.”
Sonderman also stated, “Until you get the litho community to get behind such a transition, and they are actually going to start making patterning cells and patterning tools that we can then begin to build the process… you really have to question when things are going to happen. Right now the lithography community is focused on EUV.”
Bob Johnson of Gartner characterized the problem: “When 450 comes into production, we’re going to be at the 14 or 10nm or below technologies… that means we need EUV, we need immersion for mix and match and we probably need dry litho, all to be economically viable. And then we ask, how many nodes do we have? How long is conventional silicon going to be able to keep going from the 10nm level…”
Brian Trafas of KLA-Tencor also emphasized the critical relationship between EUV and 450. Some of the challenges to date as an equipment manufacturer have been what is the design node, what is the timing, when should I start to invest…. This will be an advanced node— less than 14nm, and as such, the products we’re building today are not going to be relevant for those types of capabilities. So the question is, when is the timing for us to do the R&D? More transparency is necessary for us to be successful in moving forward with 450.”
Fortunately, key stakeholders are working through many of standards and specifications necessary to support a wafer size transition. Unfortunately, a credible or broadly-accepted 450mm wafer size transition scenario that validates overall economic benefit for the industry has yet to materialize. Many equipment companies and their suppliers remain skeptical about the business implications of a wafer size transition and uncertain about timing and the funding for necessary development.
Leaders in the industry remember the difficulties in rolling out 300mm wafer size transition, and this occurred without the specter of a companion technology shift on the level of 450 and new transistor designs. They are rightly concerned that the industry needs a clear and coordinated process for planning that takes an innovative look at new funding models. The question remains if such a process can begin in earnest with EUV production roll-out still uncertain. Many are saying, “EUV first, then 450mm.”
September 7, 2011