Synopsys and STMicroelectronics Accelerate 32-Nanometer Readiness Delivering Optimized Standard Cell Library and Route-Rule Validation in IC Compiler

Synopsys Expands Confirma Hardware-assisted Verification Solution with the HAPS-A31 System

STARC to Deploy Synopsys IC Compiler's Zroute and Clock Mesh Technologies in STARCAD-CEL

Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2008

Mike Eftimakis, Senior Product Manager ARM

Stéphane Bailly, Senior Business Development Manager Leti

Louie de Luna, Director of Marketing Aldec

What Would Joe Do? by Peggy Aycinena Real Intent: Leveraging on Investments

IP Showcase by Peggy Aycinena The Cognitive Era: Don’t be fooled, it’s already over

FPGA Engineer for Teradyne Inc at San Jose, CA

Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA

Field Application Engineer for Teradyne Inc at San Jose, CA

Senior Front-End RTL Design AE for EDA Careers at San Jose, CA

Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom

Analog Hardware Engineer for Teradyne Inc at San Jose, CA

Decoding Formal Club Meeting Hosted by Oski Technology to be held September 26 at The Conference Center in San Jose at 2099 Gateway Place, Suite 560 San Jose CA - Sep 26, 2017

CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017

DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017

11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017