Synopsys and STMicroelectronics Accelerate 32-Nanometer Readiness Delivering Optimized Standard Cell Library and Route-Rule Validation in IC Compiler

Synopsys Expands Confirma Hardware-assisted Verification Solution with the HAPS-A31 System

STARC to Deploy Synopsys IC Compiler's Zroute and Clock Mesh Technologies in STARCAD-CEL

Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2008

Brian Shumaker, DVT Solutions/Bill Rosas, Signal Microwave DVT Solutions

Sharon Cohen, President, Orbotech West Orbotech

Yih-June Liou, VP of Operations Anaglobe

ESD Alliance MSS Newsletter for Q4, 2016

What Would Joe Do? by Peggy Aycinena Simon Davidmann: A re-energized Imperas Tutorial at DAC

IP Showcase by Peggy Aycinena Austemper & Functional Safety: The Alchemy of Modifying Design

LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA

Senior Front-End RTL Design AE for EDA Careers at San Jose, CA

DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA

LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA

11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017

25th International Symposium on High Performance Interconnects (HotI 2017) at Ericsson Santa Clara CA - Aug 28 - 30, 2017

DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017

SMTA International 2017 at Rosemont IL - Sep 17 - 21, 2017