Aldec Launches ALINT-PRO-CDC Delivering Comprehensive CDC Verification Strategies for SoC and FPGA Designs

Aldec Delivers Unprecedented Scalability and Verification Acceleration with the Latest Release of HES-DVM™

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in Coverage

Lynnette Colby, Global Product Manager Kester

Sam Chitwood, Sr. Principal Product Engineer Cadence

Richard Heimsch, Director Super Dry

ESD Alliance MSS Newsletter for Q4, 2016

What Would Joe Do? by Peggy Aycinena Upverter’s Zak Homuth: On-demand Engineering to Assist Design

IP Showcase by Peggy Aycinena SmartFlow: The Importance of Export Compliance

LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA

LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA

Applications Technical Support Engineer for EDA Careers at Freemont, CA

Design Engineers PDK Parameterized Cells ( P-CELLS) SILICON VALLEY for EDA Careers at San Jose, CA

MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017

SEMICON West 2017 at Moscone Center San Francisco CA - Jul 11 - 13, 2017

11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017

DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017