EDA Weekly

The State of IP

High Level Synthesis Has Come Of Age

ANSYS turns 40!

DAC 2010 Report from the Floor

WORKS IN PROGRESS: The Economy & EDA

Silicon Valley Residency Not Required

The Economy, Semiconductors, EDA, & Intellectual Property

Workshop for Women in Engineering Design

All About EVE

Increasing The Level Of Abstraction Of IC Design

Agilent EEsof EDA – Part II

Static Timing Analysis Is Not Staying Static

Altium Limited – Focus on the Americas

A look at EDA in 2010

Agilent EEsof EDA – Part I

An Oasys Grows in the EDA Landscape

Virage Logic – On the Move!

The Best of 2009 – EDA Weekly Magazine and Press Postings

MAD Progress

Credibility

The Role of Business Planning

What is Different at Magma?

Roundtable: Virtualization & Simulation

It’s the Customers...

2009 Kaufman Award – Dr. Randal Bryant

Like Father Like Son

The Role of a Chief Technology Officer

DAC: A Standing Ovation for All …

Autosar and VSA from Mentor Graphics

Bryant the Beer Guy & Your Plans for DAC

Tanner EDA, Twenty Years and Counting

Popcorn at DAC, Azuro’s CTS, Lotsa news, Cooley’s War

Lynx, For Engineers by Engineers

DATE’09: Pousser ou Tirer à Nice

How to Compete Against the Big Three

The Aart of Analogy Revisited

The Future of EDA and the Semiconductor Industry, One Man’s View

Bee in the Bonnet, Bug on the Loose

You Can Never Have Too Much Performance

EDA: Dead or Alive?

Sequential Analysis

Jim Hogan, 2009, and the Audacity of Design

Envis - Low Power

The Best of Times, The Worst of Time: Part 2

Computational Lithography

The Best of Times, the Worst of Times: Part 1

SiP or System-in-Package

EDA: The Promise & The Challenge

SpringSoft a major EDA company with an interesting name and a more interesting business model

Blood Sport – Securities & Security

Tensilica and Customizable Processors

The Summer of Our Discontent: War Games in EDA

“Blue Ocean Strategy” + OVP (Open Virtual Platform)

DAC 2008 – Trepidation to Triumph

Elastix Clocks Reduce Margins. Landing in Barcelona.

Buzz@DAC & Kuhl@CAL

A View of Semiconductor IP from Synopsys

IP Standards: No room for Mr. Nice Guy

A Busy Day for Magma Design Automation

DATE 08: Musings von München

Closing the Verification Gap.

First 4 weeks of Shock & Awe … then DVCon

Does the Industry Need Another P&R System?

Fireside Chat: Rick Lucier & Jim McCanny

What if a Marketer From Outside EDA Were to Run an EDA Firm?

Apache Design Plus Optimal Equals?

Noble Grenoble – Savage & The Golden Age of IP

Can One of the Big Three Compete in a Market Dominated by Others?

Brown Bag Lunch: Sanguinetti & Sandler

Can a Firm Prosper or Even Survive, If It Gives Away Its Product?

Cappuccino & Creativity: Sangiovanni-Vincentelli, Sentovich, and Szymanski

CADENCE DFM - WYDIWYG

Lessons Galore from Four on the Floor

Agilent EEsof, High Frequency Leader

September Uptick

Are EDA Companies Getting Fair Value for their Software?

Hot Chips, Cool Books, Brainiacs & Workaholics Abound

Helpful Advice for Entrepreneurs. Also post-silicon validation, debug and in-system bring-up from …

Jim Solomon: Burning Intellect, Restless Man

It’s the Network Stupid, the Network-On-Chip, that is.

Nanotechnology – Science vs. Engineering

Are We There Yet? ESL with CoWare

DAC 2007 Part 2: Monday Tuesday Thursday Wednesday

Mentor Graphics – A New Strategy for Semiconductor Intellectual Property

EDA Inside: From Late Republic to Imperial Zone

High Frequency – Applied Wave Research

DAC 2007 – Perceptions of Primacy in Pleasantville

Visual Architect and Development System for Architectural Exploration and Performance Analysis - …

DAC's Dynamic Duo: Marie & Pat Pistilli

Timing and Signal Integrity – CLK Design Automation

DAC & DFM – Once More, with Feeling

Patent Licensing – MOSAID Technologies

DATE 2007 Part 2 – Special Days, Frustrating Hours

Device Native Verification of FPGAs - GateRocket

DATE 2007: Secrets et Surprises à la Côte d'Azur

Virtual Hardware Models - Carbon Design Systems

Dr. Tom Williams – A Lifetime of Achievement

Dassault Systemes/ ENOVIA/ MatrixOne/ Synchronicity PLM for EDA

The Cleansing of Iximché

Fiscal Year In Review

EDA in India

Characterization – Altos Design Automation

EDA Rising - Cool, Calm, & Collected

Fast-SPICE with Nascentric

Roundtable: Is IP Really that Bad?

Retrospective and Perspective on Printed Circuits – Happy Holden

Thanks for the LNV Memory

TotalRecall from Synplicity

Lamentation & Loss

Changes at MoSys

Making a List … Checking it Twice

Model Based Approach to DFM – Clear Shape Technologies

ESL 2.0 = EDA 4.0 … Continued

ESL 2.0 = EDA 4.0

Stock Option Backdating

Cal vs. Stanford: EDAC vs. Itself

Role of Marketing - Jeff Roane VaST Systems Technology

Dr. Robert Dutton - The Father of TCAD

Chipidea - Analog and Mixed-Signal IP

Verification Test Plan: The Book

MathWorks: Simulink HDL Coder

The Age of Enlightenment

Synopsys & SystemVerilog Verification Methodology Manual (VMM)

Midnight at the OASIS

Mentor Calibre nmDRC

SJSU's Dr. Belle Wei - Shaping the global citizen

Calypto - Equivalence Checking

Letters to the Editor: DAC et al

TSMC's Reference Flow 7.0 and DFM Initiative

DAC 2006: As the world turns, the pendulum swings

Forte Design Systems' Forte

Buzz@DAC.2006 v2

Standards - IP Arena

The Business of DFM

Bluespec - ESL Synthesis

Your UML Tutorial

- UML, XML, ESL, MATLAB & Simulink, too

Space Cowboys -- The Builders & The Dreamers

PCB Update

Thought Leaders -
3 men, 3 minds, 1 industry

Formal From Spec to Sign Off - Real Intent

Regional Advantage: Part 2

- Pitting Belgium's IMEC against California's U.C. …

Optimization - Athena Design Systems

Regional Advantage: Part 1

- Pitting California's U.C. Berkeley against …

Visibility Enhancements – Novas

DATE 2006: Between Gemütlichkeit und Angst

Yield Analysis Automation - LogicVision

Please Don't Take My Blackberry Away- RIM Vs NTP

RoHS and WEEE - EMA Design Automation

Ponte Solutions - Design for Yield (DFY)

Format Wars, Overseas Investment and Apple iPods

Zenasis Technologies – Hybrid Optimization

Intel Unveils Brand New Image

Kilopass Finds a Niche in Embedded Non-Volatile Memory (NVM)Technology

Mentor's Expedition Enterprise Flow

Return on Investment

Bridging the Gap

Intellectual Property Developments

The Optimal Solution

IPOs

Another Fine Kettle of Fish - Qualcomm vs Broadcom

Stealth Strategy - Apache Style

Automotive Solutions from Mentor

TCAD - Technology CAD

The Case of the Missing Via: Sequence Design

DIAMOND in the Rough?

Catching Up with MIPS

New Physical Verification System from Cadence

Structured ASICs ala eASIC

Who Is Using ESL and Why?

High Frequency Merger

Power Integrity with Sigrity, Inc.

Power Reduction wth Golden Gate Technology

Rambus XDR2

What Will My Chip Cost?

Bomb Detection

Oasis

AMD sues Intel

Altium - Opening A New Umbrella

OCP-IP

Kathryn Kranen- Jasper Design Automation

VaST Systems Technology Crossing the Chasm

Magma-Synopsys Litigation

Mentor's Questa Verification Products

Magma's Cobra

EDA Week in Review

Interview with Sandipan Bhanot CEO of Knowlent

Interface, Integration, Concurrency

Automotive Electronics

Theft of Trade Secrets

State of Basic Research Funding

Analog

Interview with Vic Kulkarni CEO of Sequence Design Inc.

Silicon Laser and Cell Processor

Interview with Stephen Maneatis, CEO True Circuits

DesignCon 2005

Interview with Todd Cutler, CEO Eagleware-Elanix

Personality Types

Collaboration

Radio Frequency IDentification - RFID

Conversation with Ken McElvain, Synplicity CTO

Future of Stock Options

Free Software

Interview with a CFO of an EDA Firm

Pirated Software

Web Conferencing, Webinars, …

India the Land of Service Outsourcing

Interview With A CEO

Foundries

More Assertions

Assertion Based Verification

Engineering Manufacturing Service (EMS)

Design for Manufacturability (DFM) Part 2

Design for Manufacturability (DFM)

Data Exchange/Interoperability

INTEL

Other PCB Design Systems

Ends and Odds

Mini DAC Review + ESL Chapter 2

EDA & PLM?

Strutured ASICs

To DAC or Not to DAC

Commentary: EDA Industry Update May 2004 -- What did the Last Quarter Bring?

Low Power Soc Design

High Speed PCB Design

FPGA Synthesis

1st International System-on-Chip Conference

Behavioral Synthesis

ESL Chapter 1

64-bit Computing Linux Style

China - The Land of Opportunity

Hardware/Software Co-verification

EDA Vendor Strategy for Acquisitions

TEST & ATE - Cost of Test

Conflict of Interests - Semiconductor IP Patent Rights vs Standards

Predicting EDA's future growth -- and, is Moore's Law dead, or has the paradigm shifted?

Where the Rubber Meets the Road

Getting More than You Pay For - Part I

From Glum to Glittering

High Priests & Gurus

Bits & Bytes

ATE and/or Embedded Test

Si2 and OCP-IP

EDA Unplugged 2003

True Circuits' Stephen Maneatis

A Day in the Life

Virage Logic's Adam Kablanian

Multi-threading

Taxonomy recapitulates ontology

Peace & Prosperity

50 Ways to Cleave to Others

Dr. Richard Newton

Testing, Testing, 123

SystemVerilog in the news (again)

Toshiba's Richard Tobias

Make New Friends, but Keep The Old

What Goes Around Comes Around

Two sides to every story

Musings at MIT

QIP & The Art of Motorcycle Maintenance

O Canada!

The State of IP

ALDEC Q3 – Verification Newsletter

Controlling Your Own Destiny – The Evolution of the Cloud: An HPC Seminar in Santa Clara, Sept. 9