August 02, 2010
High Level Synthesis Has Come Of Age
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Gabe Moretti - Contributing Editor


by Gabe Moretti - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


The need to manually re-implement a design at a lower level of abstraction has been the greatest obstacle to correct and efficient electronic design. This need was the major obstacle to the growth of system level design in EDA. Architect have for many years evaluated algorithms using programming languages like C and C++, as well as the M-language for MATLAB or the Simulink system simulation environment. But, once the algorithm was proven correct, designers had to code it using Verilog or VHDL before it could be implemented in silicon.


The problem was obvious to many, yet it continued to be an obstacle for many years. Those of us who have been in this industry long enough remember Silicon Compiler, the first company in the late eighties to try to develop a solution to the problem. Other companies followed it in the nineties. A market segment was invented with the unfortunate label of "Behavioral Synthesis". The idea was that since one could write a program that described how a system behaved, or should behave, it must be possible to develop a tool that translates such "behavior" into a language at the register transfer level (RTL) that could be synthesized into a network of gates. The problem was too general,
the tools developers too ambitious, and once again the fruits of the labor of companies trying to enter this market never reached commercial maturity. What was needed was a narrower focus.


Gary Smith in his Wallcharts of EDA tools and vendors, call this market sector ESL Synthesis, as it is a proper subset of the ESL market. Most vendors have now chosen to call it High Level Synthesis (HLS). As with many names created by the marketing departments of EDA vendors, this name is also not as precise as another could have been. The "high level" synthesis tools provide either Algorithmic or Architectural synthesis as opposed to three "low level" synthesis markets; digital, analog, and physical. So, I prefer Gary Smith's name, since at least it does identify a well defined portion of the ESL market sector. But my preference has lower priority than the commonly used term.
Thus I will refer to the market sector as HLS.


How High Level Synthesis Became Reality


This subject can justify a book or two, so I will just highlight the points I believe were salient in the development of this market sector. I believe that the growth of cable based computer to computer communication made possible, among other things by the popularity of Cable TV, was a key contributor to the growth of the internet. And this growth required a great expansion in digital signal processing (DSP) applications. These applications have two characteristics that make them a good target for synthesis: they are algorithmic intensive, and are implemented in digital circuitry. And, moreover, they can be implemented in FPGA devices, a fact that widens considerably their market.
Of course this was followed by wireless applications, both at the local (home networks), and global (cell phones, and satellite communications) level. These required even more complex systems that needed architectures that took both hardware and software into consideration. Architectural design was no longer a luxury: it became a requirement.


It became imperative to be able to translate these design descriptions into VHDL or Verilog. Starting with DSP applications was a simpler task, one that EDA developers could solve. And solve they did. In fact, as part of the solution, Synopsys invented a new language, called SystemC, that extended C++ with classes that were particular to hardware architectures. Mathworks, the owner of MATLAB, was both slow in recognizing the potential of the market and had not learned the power of opening the MATLAB language and making it an IEEE standard. The industry was quick to embrace SystemC, to form a consortium around it (Open SystemC International, OSCI for short). SystemC, of course
grew to provide a solution to system level design addressing many more applications than just DSP, and has seen remarkable growth in the last decade.


Today, when people talk about System Level in EDA, talk about C, C++, or SystemC. Architects can now use C and its derivatives to develop algorithms, to verify system architectures, including hardware/software tradeoffs, knowing that their work will not be an isolated effort, but the beginning of product implementation. There are a number of vendors who now offer effective tools to synthesize an architectural description into Verilog or VHDL.


Vendors and Their Products


Gary Smith just before DAC published his 2010 Wallcharts and I used the information as my guide to this market sector in order to provide a brief description of the vendors and the products they offer. The choice of which vendor to cover in this section is totally mine and is based on my understanding of the capabilities of the products offered and the market segment I think the company targets. There might be omissions, both in this article and even in Gary's chart. In this case, I offer my apology and value corrections directed to me.


AutoESL is a company founded in 2006. Its headquarters are in Silicon Valley but its development center is in Los Angeles. The reason for this split is obvious. You want to be where the action is and you also want to be close to the source of your technology. In this case the source of the technology is UCLA, an institution with a very strong Computer Sciences department (I earned my M.S. there). What I find interesting about the company is that none of the developers of the technology embodied in the product is a member of the company executive team, which is made up of Silicon Valley veterans. The originators of the technology, and indeed the founders of the
company, are Dr. Jason Cong, Dr. Yiping Fan together with Dr. Zhiru Zhang. Dr. Cong is still at UCLA, while Dr. Fan and Dr. Zhang are now with AutoESL.


The product,
AutoPilot comes in various versions specifically targeting ASIC or FPGA families. This tool looks very much like any other synthesis tools. It takes as input constraints and directives together with the system description in either C, C++, or SystemC. The outputs are the RTL description of the circuit, a wrapper for simulation using the original architectural level test bench, and a file containing the script with constraints for logic synthesis. ModelSim from Mentor and Active-HDL from Aldec are the simulators supported by the FPGA vendor specific versions of AutoPilot.


Axilica is a British company with roots in the Electronic and Electrical Engineering Department of Loughborough University. The University is well represented in the company executive team where three of the five executives are still associated with the university. For many years Europe has been at the forefront of system level design, experimenting with both new languages and new technology, often with the help of either the European or national governments funds.


UML, which stands for Unified Modeling Language, is a system design language that has been well received in many application areas, especially software engineering. In the EDA market many of our leading language architects have expressed the opinion that UML can be effectively used for both hardware and hardware/software system design. US based EDA vendors have still to fully embrace UML, but empirical use of the language is growing, a sign of at least localized success in its use for hardware design.


FalconML is Axilica's product that allows users to produce a Verilog or VHDL RTL description of a circuit starting with its UML representation. The product takes UML as input and generates RTL through an intermediate stage where UML is translated into either SystemC or C++. The use of C++ allows the use of FalconML for hardware/software co-design, since the embedded software part of the system can be expressed in C++.


The intermediate generation of SystemC and C++ is not just for internal convenience. In fact users can use the files for system level simulation of the design. FalconML supports TLM style modeling which increases simulation speed and simplicity in result analysis as well.


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-- Gabe Moretti, EDACafe.com Contributing Editor.


Reviews:
Review Article
  • Re: High Level Synthesis Has Come Of Age August 02, 2010
    Reviewed by 'Zack63'

    You should have mentioned that some tools are true synthesis tools, while some of these are really "parametric blocks"  e.g. the tools from Matlab and Synopsys Module compiler, Synplify DSP are not true synthesis engines.  There is behind the scenes structures which are modified via parameters.


    Other tools e.g. Catapult, C2S, Forte, AutoESL, are true synthesis engines, where you can create arbitrary hardware from an input description + synthesis directives.


    Also, you should have mentioned that Catapult is the dominant C Synthesis tool for many years in a row.  Mentor was an early maker of High level Synethsis tools, not late to the market (they just didn't have an RTL synthesis tool other than the ones aquired from Silicon Compilers)





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  • Sr PV Mgr August 02, 2010
    Reviewed by 'Stefen Boyd'
    The title grabbed my attention, but the typos and disorganized flow ended up leaving me disinterested and disappointed.


      One person of 3 found this review helpful.

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  • EDA Consultant August 02, 2010
    Reviewed by 'Daniel Payne'
    Gabe,
    Thanks for the overview.
    I worked at Silicon Compilers from 1986 through the Mentor acquisition. We never considered our tools High Level Synthesis rather it was an environment that had:
    * Many configurable logic blocks (SRAM, Datapath, Muliplier, IO Pads, Random Logic, ALU, etc.)
    * Place & Route
    * Floor Planning
    * IR Drop Analysis
    * Package editor
    * Cycle based simulation
    * Transistor-level static timing analysis
    * Logic Synthesis
    * ATPG
    * Schematic Capture
    The Genesil product line was dropped by Mentor, although the GDT product line along with Lsim lived a bit longer at Mentor.

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