April 07, 2008
A Busy Day for Magma Design Automation
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February 27th was a busy day for Magma Design Automation. They announced they had acquired Sabio Labs, introduced Titan full-chip mixed-signal design, analysis and verification platform, and launched QuickCap TLx, adding advanced transistor-level extraction support to its gold-standard 3D capacitance extractor. I had an opportunity to talk about the first two items with Ashutosh Mauskar, VP of Business Development at Magma.
Would you provide us with a brief biography?
I have been with Magma for the last nine months. I have been in EDA for 16 years. I have three patents and a master’s degree in EE. I have worked for major EDA companies.
Cadence and Synopsys
What is your current title at Magma?
I am Vice President of Product and Business Development.
What does a VP of Product and Business Development do?
I am responsible for business development activities for the entire Titan platform; product marketing, product rollout, development plan, all that stuff
Can you tell us about Titan that Magma recently announced?
Magma has announced our new product platform for mixed-signal. The name of the platform is Titan. The reason for that is pretty simple because if we look at the history of Magma, we have brought automation to the digital side. We introduced physical synthesis basically combined synthesis and physical synthesis together. If you look at the analog side, things have not really moved in that direction for a long time. If you look at the state of the art of analog technology, you are talking about 180nm and 130nm. If you look at the state of the art of digital technology, it is 45nm and 32nm. The reason for that is very simple because there is automation on the digital side. You bring your RTL and you synthesize to place and route. You have turnaround time from RTL to netlist in two or three days or perhaps a week at the most. But if you look on the analog side, the process migration of a design could take anywhere from six to twelve months depending on the complexity of the design. And then additionally the chips are mixed-signal nowadays which means integration of digital and analog full custom can take another four to eight weeks. If you look at the productivity of pure digital design and the productivity of mixed-signal design, the long pole in the tent besides integration are analog full custom as well as the design of analog full custom. There is no automation for that yet. There are reasons why they are not there. If you look at the way analog custom design is done today, you start with system design. You basically draw some Excel, AMS sort of specification. You verify these specs using C, MatLab or SPICE or something. Basically when you start with circuit design you have code where your system design works, then you restart your work drawing from schematics, writing specs from MatLab, Excel or paper and then capture the schematic. You SPICE the schematic making sure that it is verified and then finally you do physical design; manual design, constraints, placement and routing, extraction so on and so forth. For every node from 180nm to 130nm to 90nm to 65nm, you have to restart doing the design each time. You have to recreate every step which is either system level or circuit level or physical level design by hand. For every new node designs have to be recreated by hand from scratch. The issues become how accurate the transition is going to be, how automated is it going to be, whether you can have any reuse, whether there is any compatibility issues and so forth. In order to take care of all these issues, it typically takes designers anywhere between six to twelve months. Automating that is a very hard problem to solve, the kind of problem that Magma likes to solve. That is why we have introduced a new platform, called Titan, which is a
full chip mixed-signal design platform. We implement complex mixed-signal designs using a single platform. It allows you to improve your productivity by orders of magnitude by delivering unprecedented integration and automation to analog design.
What are the different components of Titan?
The key Titan technology components are essentially standard things that you would find in a full custom analog design environment which are schematic editor, simulation environment, IP process migration.
I am sure that you have heard that we recently bought a company by the name of Sabio Labs. It is an IP design as well as automation company. It allows us to take high speed components such as SERDES, ADC, DSC, PCI Express or PLLs and model them in one process using process independent circuit equations and migrate to another process node such as 130 nm to 90nm to 65nm using those process independent equations and providing you the flexibility to explore different options when you do the process migration.
Editor: Magma acquired Sabio Labs. The purchase price was $17.5 million plus possible additional payments up to $7.5 million based upon contingencies. Investors in Sabio Labs include Andy Bechtolsheim. The CEO of Sabio Labs is Mar Hershenson. She did ground breaking work at Stanford University under Professors Boyd and Lee in the area of automation of analog circuit design using convex optimization. In 1999 she and Professor Boyd formed Barcelona Design Inc based on that work. She became CEO and later shifted to CTO. Barcelona was notable for having raised $44 million in venture funding, for having Joe Costello as chairman, and having a Web-based pay per use business model.
Barcelona had two products, namely, Picasso Op-Amp Design and Dali PF Passives Designer. The technology automatically generated an optimized netlist from user-defined specifications. The company encountered difficulties and despite changing strategic direction and adopting a more traditional EDA business model the company ultimately closed its doors.
In our layout editor we have a shape based router. We have integration. That is the important part. This is a single platform that allows you to look into your digital as well as your analog pieces together. In a single canvas you have full on layer visibility, the digital part as well as the analog part. That is something that has never happened before. That is something that is very unique to the platform.
In this IP migration, if I already have an analog design and want to migrate to a new process node using the technology from Sabio Labs, do I have to convert that existing design into these circuit equations?
Yes! There is a one time issue of conversion of existing IP. And that is the beauty of it. We are basically freeing up analog designers to create ever new IP using their inherent artist techniques for analog designs. There is no way we can always replicate that. Obviously designers have years and years of experience. What we really want is for analog designers to be free to create new designs as opposed to just migrating the same designs over and over again. The idea is that if you create a PLL, you capture that PLL at one process node, say 180nm, you capture the topology of the PLL in terms of equations at the beginning of the process and then you can just migrate seamlessly from
one node to another to another. That’s the whole point of doing that.
But there is a one time conversion for an existing design from its original form to these equations.
Yes! In fact when we talk to our customers that is what they want. Obviously we provide standard templates for PLLs, SERDES and stuff like that. That is not very helpful because each analog designer takes pride in the fact that he or she has tuned the circuits to their own satisfaction and for their own requirements. It is actually a good thing we had to do this because that way they can capture their own specifications and topology.
What is special about Titan that you won’t find in other platforms?
We have FineSim integrated simulation environment, IP process migration in terms of automation. We have integrated the digital and custom analog flows seamlessly. Along with FineSim which is a full SPICE and fast SPICE simulator, we have integrated full Talus which is our digital design solution. We have integrated Quartz DRC and Quart LVS verification solutions. Last but not least the speed and capacity of the platform is pretty high. We have seen improvements up to 10x over existing solutions. It allows designers to integrate quickly the entire chip. There is a smooth migration path because it is important that designers who have
labored for years and years want to have the ability to smoothly migrate from existing environments to Titan. We provide that path for our customers.
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-- Jack Horgan, EDACafe.com Contributing Editor.