November 19, 2007
Can One of the Big Three Compete in a Market Dominated by Others?
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In my last editorial I discussed the case of how a firm (Ciranova) could make money, if it gave away its own product. This time the issue is how does one compete with a significant player who is offering if not free, very inexpensive tools? Xilinx and Altera dominate the FPGA marketplace. In fiscal 2006 they had revenue of $1.84 and $1.3 billion respectively. Both firms offer tools for designing and developing with their FPGAs. Mentor Graphics believes it can compete by offering vendor independent physical synthesis with advanced capabilities like automatic incremental physical synthesis and resource management. Mentor has recently introduced a new offering called Precision RTL Plus
with these capabilities. I had an opportunity to discuss this situation with Daniel Platzer, Product Line Director for Synthesis Products
Would you give us a brief biography?
I started my career at Daisy. I started as a hardware engineer. I think I was one of the very first ones who actually used CAE tools for the purpose of designing hardware. At that point it was PMX, some accelerators and stuff like that. Then I moved within Daisy to technical marketing and product management around PLDs and behavioral languages. Daisy had a proprietary language called Able and we had a product called PLD Master. My career back then was around the original EDA tool for programmable devices. I did some kind of major detour to networking companies and to e-learning. I actually started my own business and was CEO for 7 years in a pioneering e-learning company (Tegrity). A
little over two years ago I went back to my childhood so to speak and joined Mentor and here I am.
What are some of the trends in the FPGA arena that Mentor is seeking to exploit?
There are some obvious industry trends. The first one is of course increased design complexity as the silicon becomes more capable in terms of functionality, speed, area and so forth. The consequences of being more complex is it runs the risk of delays and being over budget. Coming from the EDA industry we are convinced that EDA tools are the best friend of the designers and their management to make sure projects are on time. The complexity means that we really do not want to cut corners when it comes to selecting tools. The second trend is that there are more advanced EDA tools. It is quite open now that companies find themselves designing with chips from Xilinx, Altera, Lattice, Actel and so forth. The reason is very simple. Altera might be the best tool for you today but maybe tomorrow or for another project you find out that Xilinx is 30% cheaper or better. As a designer or management you need to retain the flexibility to move from one silicon to another, from one vendor to another. It is becoming more and more apparent that a good way to ensure that an engineer can actually do that is that you need vendor impendent tools. The designer community and the management are less and less thinking of using vendor specific tools because these vendor tools are not about the flexibility to move from silicon to silicon. The third trend is there is more ASIC prototyping. More than 50% of complex ASICs are being prototyped. Prototyping is all about taking the ASIC and trying to prove the design in FPGA platform. The truth of the matter is that there are not too many tools that are designed from the ground up to support the needs of ASIC prototyping. For example, these vendor tools do not necessarily do gated clock conversion, designware support and so forth. So if you are in the business of ASIC prototyping, you want to make sure the FPGA synthesis support the ASIC prototyping flow. The last trend in the last 5, maybe even the last 10 years, is that big companies realize that selecting the best tool in class without paying attention to whom you buy from will end
up with the situation where you have too many vendors which means less buying leverage, multiple points of support and interoperability issues. Therefore, big companies are trying to reduce the number of their EDA vendors.
Today, are FPGAs used mostly as a component in the final solution or as a prototyping tool for ASICs? Is it 50/50 or something else?
Most of the design starts are end products. It’s not 50/50. I would say as a guess that 30% are in ASIC prototyping. But no one really knows the numbers. But it is significant either way.
How does Mentor fit into the picture?
Mentor is clearly the EDA leader in servicing the FPGA design community because of one simple fact. In order to have an FPGA solution you need to have four basic components. These are design entry, simulation, FPGA synthesis and PCB tools. There is no other EDA company in the world that has these four basic components. Without these four components, you do not have a complete solution. Therefore Mentor is clearly the leader. That is not to say that we don’t have lots of other tools for hardware/software integration, high level synthesis and so forth.
There are over 1,000 companies using Mentor’s FPGA synthesis products. The reason we are seeing an increased business is that more companies are realizing that vendor independent synthesis is important. They realize this especially after they have to undergo a painful switch from one vendor to another. If you look at overall vendor independent synthesis, it is Mentor and Synplicity. Roughly judging by the size of the install base and the number of users is approximately the same.
Synplicity is a company with annual revenue in the $60 million to $70 million range. Is Mentor’s FPGA revenue about the same?
No. We have less revenue. The reason is very simple. When Mentor is selling FPGA synthesis, it is almost always as part of a basket of tools and therefore the business terms are much more favorable for the customer. The customer ends up paying much less for Mentor FPGA synthesis as opposed to the solutions from Synplicity. So while the number of seats is the roughly the same, Synplicity is generating higher revenue because it costs the customer more money per seat.
What are the issues that need to be addressed?
Every state of the art FPGA synthesis needs to address three stages. The first stage is to start right by supporting industry standards for the input of HDL and constraint filers. If the tools do not support standards, it will be very difficult to actually take and reuse designs successfully. The second one is the engine itself. Synthesis today needs to deploy the latest and greatest in optimization. The third one which is hardly the case today is to be able to push a button and meet aggressive design goals. You end up having in many cases especially in large and complex designs that you are not quite there and you have to start engaging in analysis and debug. Today FPGA
synthesis needs to be very strong in the analysis and debug process
The first thing that comes to mind is language support. We are convinced that we (Mentor) are the leader in FPGA synthesis language support. For example, if you look at System Verilog it has increasing popularity not only for verification but also for design. When it comes to supporting synthesizable subset of System Verilog Precision is by far the leader. No one else actually comes close. Whenever, we do market education and seminars, the System Verilog to synthesis is always over booked.
Of course it is also important to support standard constraints because a design is not just HDL, it is also the constraint file. Also important today is the fact that HDL is not only hand coded but also generated by high level synthesis and some other tools. It is important that synthesis supports the flow generated by neighboring tools. Being Mentor we have more neighboring tools around synthesis than anyone else.
State of the art synthesis needs to support technology independent inferencing. All kinds of gated clocks are extremely important for ASIC prototyping. ASIC prototyping is all about taking the design from the designers and very quickly synthesize it into FPGAs. In the ASIC arena there are a lot of gated clocks and sometimes Designware. If you do not have a gated clock conversion, your tool will not be successful in achieving reasonable performance.
The last one is that when you pushed the button and got close but not quite there, the tool needs to show you where the critical paths are. And it needs to show you in different ways including graphical views so you can actually track and see the reason, you can cross probe from timing reports to the source so you can understand which line in the source is actually the offending line that created the critical path. There is the missing constraint report, the domain crossing report. All of those interact. You do not have to re-synthesize them from the beginning. All of that capability is
important for the designer to be able to identify the problems so that he/she can fix them. In an objective customer satisfaction survey done by the FPGA Journal, Precision was voted the one with the highest satisfaction for analysis by a synthesis tool
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-- Jack Horgan, EDACafe.com Contributing Editor.
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