October 22, 2007
Can a Firm Prosper or Even Survive, If It Gives Away Its Product?
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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Can a firm prosper or even survive with a strategy based on giving away their product? In the old days Gillette did very well giving away razors and selling the blades. Today telephone cell phone carriers (Verizon, AT&T, Sprint, etc) give away or at least steeply discount cell phones in exchange for signing service contracts, typically two year contract with early termination fees. Google and Yahoo! provide free services and derive revenue from advertising, an approach that major TV networks and some print media have used for years. Similarly, this website distributes free content and generates revenue from advertising.

Ciranova, a firm that started in 2002, adopted a new business model that has them giving away their PyCell Studio product via Internet download. I had a chance recently to speak about this with Ciranova’s new CEO Eric Filseth.

Would you provide us with a brief biography?

A long time ago I was an analog design engineer. I worked for National Semiconductor on op amp design. I went to work for a small EDA company called Analog Design Tool which was acquired by Valid which got acquired by Cadence. So I ended up working for Cadence. If you count the two acquisitions I worked for Cadence for just under 11 years primarily in the analog area. I was marketing manager for the analog tools area. I left Cadence at the end of 97. I worked for several digital startups. One was Sente which became Sequence. The next one was Silicon Perspective. It was acquired by Cadence at the end of 2001. I’ve been working for Cadence since then. I left a month ago. Monday this
week was my two week anniversary.

Happy anniversary!

It has been an interesting journey. I spent the first bunch of my career in the analog area and the last bunch of years in digital. Most recently at Cadence I was Corporate Vice President of Marketing responsible for all the digital stuff: RTL through mask, place and route, formal verification. All that kind of stuff. Mainly coming to Ciranova is sort of going back to my roots in analog.

What caused you at this point in your life to go from the largest EDA company to a small startup in a small niche market?

First of all I think at some level it was a reasonable time for me to look for doing something else. Our mission at Silicon Perspective was basically to rebuild the digital business at Cadence back to industry leadership. We did that. Cadence had some difficulties in the digital area in the late 90’s. We rebuilt a very strong and industry leading capabilities for RTL to GDS. It was kind of mission accomplished. I’m very proud of the work we did there. I saw this as a new kind of challenge.

One of the things I learned from working in both the analog and digital areas is that the digital area is much more automated then the whole custom slash analog area. In the digital domain engineers say “I would like this PCI Express design but I want it with 5 new features and I want to move it to 55nm technology.” They say that and a computer goes and does the whole thing, whereas in the analog world it is all still done by hand. You have senior design engineers redesigning, very specialized people doing lots and lots of work. A lot of people would say it is very mundane work moving shapes and rectangles around the screen. Stuff is just vastly more automated on
the digital side. I think that there is a vast opportunity to go back and revisit the custom world and do a lot more automation. I thought that was a real intriguing opportunity. Ciranova has interesting technology to do that. So I thought this is something that could be pretty exciting.

What is a PCell (p-cell, PCELL)?

A PCell is a piece of code that an engineer writes which tells a computer how to draw a transistor. Writing those programs (and each one is dozens to hundreds of lines of code) is quite laborious. If you change your silicon process you have to do the PCell again. If you have a 65nm transistor and you want that transistor to run in 45 nm technology, you have to do the PCell all over again. Each type of transistor has its own PCell. If you want a PCell that runs in both a Cadence system and a Synopsys system for example, you can’t have that. You need a different one for each of those. So people end up having to spend lots of time and effort making PCells in order to draw
transistors. Typically what happens is your foundry provides them or if you are a large semiconductor company in a lot of case people will do their own, have big teams of people doing this over and over again. This is one of the things where we think there is real opportunity to make it more efficient.

For PCells what is a supermaster, a submaster and an instant?

A super master is the code, in our case PyCell code. That code exists on disk somewhere in a library. When a chip designer lays down a transistor with a width of 2 and a length of 3 that becomes a submaster. A submaster is a particular representation with a specific set of parameters. If they use a width of 2 and a length of 3 over and over that is a submaster with lots of different instances.

How does a PCELL relate to a PDK (Process Design Kit)?

A PCell is a particular library element within a PDK. A PDK is basically a set of files that a foundry provides its customers so that the customer can do transistor level design. PCell is a major component of a PDK. PDKs contain a few other things like schematic symbols, DRC rule decks and other files necessary to do analog design.

PCells have been around a long time. What problem was Ciranova trying to solve? What issues needed to be addressed?

A good question. PCells have been around almost 20 years. They were pretty revolutionary for their time. We are down in a very low level discussion of automation here. Before PCells engineers literally drew transistors by hand. A PCELL partially automated that. That was a good deal for its time. But PCells have a lot of limitations. The principal ones are that they are not portable from process to process. Each silicon technology needs its own set of PCells, even if the transistors are otherwise identical. If you have a 90 nm transistor, a standard MOS set, and you want to take your design using that transistor into a 80 nm half node technology you need to do all your PCells over again. That’s because the way PCells are done is that they hard code processing information into the PCELL. That’s a major limitation. The second one is that people have a lot of kinds of devices that are not easily represented in PCells. Say you want to do something like a spiral inductor that will have complex via structuring inside of it. It is not very easy to do that in a PCell. So people end up drawing by hand. The third problem is that if you look at all the custom systems out there on the market, they all have a different mechanism for representing how to draw a resistor. Cadence has one way of doing it, Mentor has a different way, and Silicon Canvas a third way. There are
potentially some other tools that will show up that will have different ways of doing it. That means if you have your library of PCells and if you want to run those transistors in a different system, you have to do you PCells all over again. What people want is a PCELL that can run in different process variations and can run in different tool flows and have enough capability so that they can describe these kinds of complicated devices that people have these days.

How do your products address these limitations?

We have developed what we call PyCells which is conceptually the same idea as a PCell, a piece of code that a user write in order to tell a computer how to draw a transistor. The advantage of using PyCells is threefold. First of all, the user writes PyCells in a modern programming language. The one we use is called Python. People in EDA are not familiar with Python but it is widely used for Web 2.0 applications. For example, a lot of Google is written in Python. It is a much more powerful language than what people are used to using for p-cells. Most of them are written in an older language called SKILL. SKILL has been around about 20 years. It is based upon LISP. It was modern in the 1980’s. It is fairly old now. If you look at Python code versus SKILL code, first you need to write a lot less code to do something in Python. Second you can produce a much more complicated structure and complicated behavior easily using PyCells rather than using PCells. The second thing is that PyCells don’t require you to embed data inside the cell that is specific to any given silicon process. That means you can use the same PyCell in multiple silicon technologies. Everything I wanted to do, shrink from 95 nm to 65 nm or if I have several different versions of my 65 nm technology e.g. my regular one, a low power version, a low leakage version and so forth I can use the same PyCell. People really like that. The third one is that PyCells are interoperable between design flows. There is an industry effort called the Interoperable PCELL Library (IPL) initiative. In fact you can visit their website iplnow.com. There a bunch of companies and we have worked together to build PyCell libraries that will work in design tools from many different vendors. The members of IPI are Synopsys,
Magma, Silicon Canvas, AWR, Virage Logic and Silicon Navigator. A lot of people involved. So that is the three advantages: a modern powerful language, process portable and interoperable between EDA design flows.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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