September 03, 2007
Are EDA Companies Getting Fair Value for their Software?
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I had an opportunity to interview Jacob Jacobsson, CEO of Blaze DFM. His company has a product, Blaze MO, which significantly reduces leakage power and thereby improve parametric yield. This fits in the design flow after tapeout and right before OPC. Near the end of the interview we discussed the issue of whether Blaze and by extension other EDA companies were deriving the appropriate amount of value for the benefits their products and services provide to their customers.
Would you give us a brief biography?
That would take two hours. As you can hear I have an accent. I was born in Sweden. My first degree was actually in languages but you can’t make a living out of that so I went for engineering and computer science. I moved to Silicon Valley in ’83 and joined the first true EDA company, Daisy Systems, where I was lucky enough for it to go public in very short order after I came. I went to Cadence after that. My background is actually as a silicon designer. I then went to work for Xilinx. I was General Manager for one of their divisions until Xilinx got so big that I could not know everyone by their first name. I ran a fabless semiconductor company called SCS. Then I
was president of Forte Design Systems that made high level synthesis tools. I was then recruited to Blaze roughly a year and half ago for the opportunity here.
Forte is an ESL company.
Yes, it is an ESL company. As ESL companies go it is somewhat successful. The company felt a need to reorient itself in the direction of an IP company rather than as an ESL company. Neither I nor the Board felt that I was the right guy to do that. So we parted as friends.
Every time I talk to a current or former ESL company executive I say that the value proposition is compelling and that industry analysts have predicted great things for ESL but the success has yet to happen. What is your explanation?
We’re not here to talk about that but I will give you some general observations. I think it is absolutely nature bound that ESL methodology will eventually prevail. I think it is more a matter of timing. The industry has been good enough in dividing and conquering design size up to now so that it has not become absolutely essential. But the day will come for ESL technology. It is more a matter the companies are there that are basically waiting to see when that happens. Some of the better companies will make that happen faster because the barrier to entry gets lower for the customer. In my opinion it will happen but the problem has not grown so big yet that it has
So there is insufficient pain at this point in time?
The pain will come. Cleary several companies including Forte believe that the pain is already there. I think we are teetering on it but it has not happened yet. Interestingly enough there is a kind of synergy between the problems we see in the back end going to 65 nm and 45 nm and the ESL on the front end. I think 65 nm systems are becoming big enough that the pain will become really high. One of the things we have observed is that it took longer to leave 95 nm to go to 65 nm. That was felt by the ESL companies.
Turning to Blaze DFM. You joined them a year and half ago. When and where did Blaze start?
Blaze DFM was formed at the end of 2005 by three people. Professor Andrew Kahng of UC at San Diego was one of the founders. His reason for founding Blaze was to exploit several of the ideas he had. He felt that DFM was underserved in the area of addressing the parametric yield issues. He joined with David Reed who is an EDA veteran most recently from Monterey. Some time before that David was with Cooper & Chyan Technologies. Also Kahng recruited Dr. Puneet Gupta who was one of his lab students. They basically exploited the ideas the professor had.
The reason for my joining was that by then they were ready to go to market and they wanted someone who had experience.
That’s why they recruited you. What attracted you to Blaze?
One of the things that Blaze did early on and I can not take any credit for it since they figured it out themselves. There are different ways of doing DFM. One way is to try and inject yourself into the manufacturing flow which is a very slow and high barrier to entry route. The other one is to fundamentally change the EDA flow by injecting yourself into the place and route or something like that which is doable but drastic changes to design flow take time to implement as well. Blaze decided to layer themselves right after you have taped out to GDSII and before you go to OPC (Optical Proximity Correction). For me it is important that this is non-disturbing to the design flow
and as a result of that it would be easy to capitalize on what the company did. Also by putting yourself there, the effect of what you do is very easy to measure. You can measure the parametric yield impact from what you do versus if you don’t, for example by doing an A to B reticle in your tapeout. There is no discussion about the value of what you do. I found all of that to be very fascinating.
According to a company press release Blaze DFM raised $10 million in March.
That is enough for us to become profitable. Given the uncertainty of the capital markets lately it wasn’t genius but we were fortunate that we could do enough in that round. We are going to use it for the best.
Is that $10 million the total funding or were there earlier rounds?
There was another round before that. That round was around $6 million.
How big a company is Blaze DFM?
We have about 40 people.
You have two products, MO and IF. Does MO stand for Multiple Optimizations?
No, it does not. When the company was formed the first idea was to do mask optimization, to make mask generation cheaper. As part of the research of the company, they realized the same technology could be used to reduce power and improve on the parametric yield that way. The MO name prevailed but the target today for that product is power reduction. The other product is called IF for Intelligent Fill which is an intelligent way of generating fill patterns on the chip.
You may have read that we acquired earlier this year a company called Aprio. We did that to get access to a lithography engine that we didn’t have in the analysis space. Later on this year we will launch a product that exploits that litho engine to improve parametric yield.
Would you expand on what MO does?
MO has a very accurate timing analysis. It uses that information about which paths in a design are timing critical and uses that to find transistors not on the critical path. For those transistors we will adjust the gate length as much as the foundry feels comfortable with. By doing that you get a slightly slower transistor, which is why you need to know the timing, but with a profound improvement in the amount of leakage power that the transistor is going to waste. We actually have published customer testimonials that the improvement in leakage power can be 20% or better.
From your website I see the approach is to add some annotation to the GDSII file.
That’s the barrier to entry argument that you use. There have been DFM companies that say the entire flow will have to fundamentally change. Maybe that will happen some time in the future but when you do that, it will delay your introduction significantly. What we chose to do is to add an annotation layer to GDSII which is picked up by the OPC flow and being used to hit another target for these transistors. Basically you have a target for the OPC saying for this particular transistor I don’t want you to hit the nominal 90 nm (or whatever) target but I want 96 nm or whatever number the foundry is comfortable with.
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-- Jack Horgan, EDACafe.com Contributing Editor.