August 27, 2007
Hot Chips, Cool Books, Brainiacs & Workaholics Abound
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Although the weather in other geographies of late has been record breaking in terms of heat, rain, hurricanes, and monsoons – here in Silicon Valley it’s been one of the bluest, mildest, most gloriously beautiful summers imaginable. Anybody in their right mind would have taken the entire month of August off just to bask in the delicious perfection of it all, but happily the work ethic is up and running in Silicon Valley.

Last week alone, saw a plethora of events. The Fabless Semiconductor Association hosted a lunchtime panel of distinguished speakers at the Santa Clara Convention Center talking about the future of innovation. The Hot Chip guys hosted a
bunch of chip-design brainiacs on the sun-dappled Stanford campus, followed straightaway by the Hot Interconnect guys. Sun Microsystems hosted customers and press alike on their own sun-dappled campus in Santa Clara to announce their new Eco-Everything initiative. Both Synopsys and Mentor kept EDA analysts and press busy with their quarterly revenue conference calls and the subsequent jubilation in the market, Cadence acquired Clear Shape, and Cadence and Mentor together announced a cooperative verification initiative.

Are all these people crazy? Don’t they ever look out the window and think about heading out to the beach with an umbrella and a good book? Apparently not, so please read on to see what’s been going over the last several weeks. (First click Print Article to see the total text w/o interruption.)


Chapter 1: Blessed are the Peace Makers – Mentor & Cadence play nice

Cadence Design Systems and Mentor Graphics announced they will standardize on a verification methodology based on IEEE 1800-2005 SystemVerilog. Per the Press Release: “The [newly announced] Open Verification Methodology (OVM) will deliver a tool-independent solution [that] delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and [will] be available in source code format … The OVM library will be open source [under] the terms of an Apache 2.0
license, SystemVerilog IEEE-1800 compliant, and portable to any simulator supporting that IEEE standard.”

“The OVM and supporting class library include foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments, and reusable VIP in SystemVerilog … Cadence and Mentor have collaborated to ensure that the OVM will run on their simulators, and will enable backwards compatibility with their existing environments, AVM from Mentor Graphics and Incisive Plan-to-Closure Methodology (URM module) from Cadence.”

Sanjay Srivastava, President and CEO at Denali Software, endorsed the move via a Press Release: "The industry is clearly embracing SystemVerilog for functional verification, and this is further accelerated with an open source methodology that offers increased interoperability within the EDA ecosystem. Portability is key, and the OVM addresses this with multi-vendor support.”

Predrag Markovic,
President of HDL Design House, offered: "The OVM offers exactly what we have been looking for: a single open, robust, and interoperable verification methodology [that] greatly simplifies our development and support processes, and will speed up the delivery of VIP and verification environment components to our customers.”

From Robert Hurley, CEO at Doulos: "The commitment from Cadence and Mentor to offer an open verification methodology rooted in IEEE 1800 with transaction-level modeling support that is interoperable amongst EDA tools and supports interoperable VIP will be matched by our commitment to support customers globally with training to allow them to get the most out of the OVM."

The implications of all of this seemed potentially profound, so it was great to chat by phone on August 22nd with Stan Krolikoski, Group Director of Standards and Interoperability at Cadence, and Dennis Brophy, Director of strategic business development in the Design Verification & Test Division at Mentor Graphics.

Stan and Dennis go way back – over 20 years they told me – and were both involved, along with Gabe Moretti and Shrenik Mehta, in the coming together of VHDL and Verilog and the founding of Accellera. Stan has also been heavily involved in SystemC, and the founding and nurturing of OSCI. What Stan and Dennis don’t know about language standards and inter-industry cooperation probably isn’t worth knowing.

Stan said, “With the coming of verification IP we all saw great promise for SystemVerilog, but we also saw the three major EDA vendors, to a greater or lesser degree, each developing IEEE-compatible class libraries. Synopsys produced VMM, Cadence produced URM, and Mentor produced AVM. This [proliferation] wasn’t helping the industry, so we started talking with Mentor about combining our assets. Some of the people [involved] at Mentor had worked in the past with some of the people at Cadence, and so it became the natural thing to work together to develop a common set of class libraries that could be made available on an open and free basis to the industry. With all due
respect to the small players in the industry, there are actually 3 [main worlds] in simulators. By creating OVM from Mentor’s AVM and Cadence’s URM, we’ve now made two-thirds of those worlds compatible.”

I asked Stan and Dennis why the third world wasn’t involved in OVM. Dennis said, “Synopsys has never wanted to go that way on the methodology side, but it’s been a natural thing for [Cadence and Mentor] to come together on this, because we look at the problem in the same way. Bringing our two bodies of work together to create OVM has not been a trivial [effort], but we also didn’t have to make radically large changes to the way we do things because we approach the problem in the same way. Now users common to both Mentor and Cadence, as well as verification IP suppliers, will get interoperability and portability in their test benches.”

I asked if this type of cooperation within the infamously competitive, contentious world of EDA was something to celebrate. Dennis said I was overstating the tension in the industry: “When two parties in the industry want to collaborate, they will. Fundamentally, we did not want to do anything in OVM that required private ways of interpreting SystemVerilog. [We used] the stock IEEE standard language, so all companies would have access [to the results].”

Stan added, “Under the Apache 2.0 license, there really will be no restrictions on what you can do with OVM. Mentor had already put AVM – a damn good piece of technology – out under that license and we were planning to go out with our Incisive Plan-to-Closure Methodology under open source, as well. Now Cadence and Mentor are providing interoperable and proven [technology] that will work with both of our simulators, [providing] great benefits across the industry to everyone including IP providers, consumers, and other EDA companies.”

“VIP is required,” Stan emphasized, “if we’re ever going to fulfill the vision of platform-based design. If we can’t get a VIP ecosystem to work, we’ll never succeed. With OVM, we’ve made sure that at the TLM-level SystemC and SystemVerilog can interoperate.”

To which Dennis added, “We’ve started to build communities that will allow VIP to become plug-and-play. The SystemC [people] have been working to define a TLM. Through OVM, Mentor and Cadence have now taken the concept and made it available in the SystemVerilog environment, as well.”

Stan added, “This ability to interoperate at the transaction level will help SystemC, [particularly] in companies where there’s mixed use of languages at a higher level.”

Similarly, Dennis said OVM will help SystemVerilog: “[Previously], companies creating VIP couldn’t afford to maintain business relationships with other companies, retarding the entire adoption of SystemVerilog. What Mentor and Cadence are doing here is to make the barriers to adoption as low as possible, and to live up to the promise of the SystemVerilog language. Also, in addition to the code, we’ll have two other important elements in OVM – documentation and a set of guidelines for the users. If users follow these guidelines, they’ll be able to interoperate.”

It all sounded so easy and sensible, I asked Stan and Dennis if there was a hint somewhere in there that OSCI and Accellera would soon become one. They both laughed out loud. Stan said, “We’re not merging! But both franchises – OSCI and Accellera – want to see the promise of SystemC and SystemVerilog [realized], and these standards are connected.”

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-- Peggy Aycinena, Contributing Editor.


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