May 28, 2007
Timing and Signal Integrity – CLK Design Automation
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Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

On May 21st

CLK Design Automation introduced the Amber™ Analyzer, a threaded and incremental static timing and signal integrity analysis solution.  The product leverages the power of multi-core, multi-processor compute platforms to execute 10 to 20x faster than conventional tools.  Incremental analysis increases throughput 100x or more over existing design flows.  I had a chance to interview
Isador Katz before the announcement.

Would you give us a brief bio?

From start to finish or finish to start?

Whichever you prefer.

Bachelors in economics from Wesleyan University in 1979. Worked as a regulatory economist for three years, working against the Bell System at the time.  Decided I did not like law but I liked technology.  So I went back to grad school at MIT.  In ‘84 I left MIT and came to work at a company named Daisy Systems.  Worked for Tony Zingale and from there for Lucio Lanza.  When Daisy began to disappear, I went to Dataquest in 1986 where I was senior analyst for electronic Design Automation.  That lasted a little more than a year.  From there I went to work at Cadence where I had a number of assignments.  For the last two years I was VP of marketing for the IC Division.  Decided to leave because I wasn’t crazy about working for my boss by the name of Gerry Hsu.  Went and worked for the Hailey brothers at MetaSoftware.  I decided I had gone from the frying pan into the fire and moved back east to work as VP of Marketing and then CEO at Chrysalis Symbolic Design.  That was from ‘95 to ‘99.  In 1999, of all things, I sold Chrysalis to guess who, Gerry Hsu.  Stayed there a couple of months and decided that it was not going to work again.  Decided to leave EDA.  From 2000 to early 2003 I was CEO of Lightchip, an optical component company that I was brought into to try and
rescue by an investor.  You can do everything you can but can’t fix a market.  So in 2003 we sold that off.  In 2003 I looked at different opportunities.  In 2004 we were actually invited back to look at opportunities in EDA which we did very quickly and came up with the idea of CLK Design Automation which we started working on in the fall of 2004.  We got funding in 2005.  That’s where I am today.

You had one curious position, namely, EDA analyst at Dataquest.  Did that experience give you any insight that you would not otherwise have had if you remained on the vendor side?

It actually gave me one profound insight that I should read my own newsletters more closely.  Your own insights that you write under pressure are often times the best ones you come up with.  In ‘87 I did two newsletters within two weeks of each other.  One was for synthesis that said this looks like a market that is going to take off.  People need this stuff.  I wrote up a forecast showing it roughly doubling every year.  The people I knew from Daisy were over there.  I probably should have gone to work for them.  I wrote the second article on something called design framework.  I said these are essential technologies to
integrate EDA tools together.  Everyone is going to have to have them in their flow but I am not sure anyone is going to pay for a framework.  So, what do I do?  I go off and work for my friends at a standalone framework company.  So read your newsletters more closely.  Sometime your first instincts turn out to be your best.  For people who live on brains sometimes that is contrary to your own thinking.

Does CLK mean anything other than clock?

Yes.  The way the company got founded was that Hal Conklin and I were invited by this VC to look at EDA.  We quickly recruited our old engineer, Lee LaFrance, from Chrysalis who had been VP of Formal at Avant!.  He said that I have the perfect architect, a gentleman named Joao Geada.  The four of us were working on it in the background.  One moment in the morning in a rare moment of lucidity I said Conklin LaFrance, Katz and Geada what about CLK DA, CLK Design Automation.  That’s it.  It has nothing to do with clocks.

What is that you are announcing?

We have two different announcements.  One is about the product Amber Analyzer, the other in the background is about the company.  The product announcement is that we have developed a next generation static analysis tool suite.  Essentially it is fully threaded, fully incremental and has a number of enhancements behind it that meet a lot of unmet requests from customers.  This is really a classic case of faster, better, more.  Faster in the sense of taking an existing foot print, do a lot more with it and then doing something radical to really improve throughput.  More is the laundry list of features that people have always been pressing vendors to have but
they never seem to get.

Where did CLK Design Automation come from?

We are backed by Morgenthaler and Atlas Ventures.  Morgenthaler is best known for investing in Synopsys.  They also invested in Chrysalis and Lightchip.  Atlas you probably know from ViewLogic and BlueSpec.  When Atlas came to us and asked us to look at EDA again, they had heard about 65nm and 45nm.  We immediately called all of our old customers and asked them what problems they were working on and needed to be fixed.  They mentioned a couple of them, some in the physical design space.  We knew those required talent on the west coasts that we did not have access to.  One of the top issues they kept coming back to was that the current timing tools simply were not getting the tools done.  Not that they are bad tools.  They were great tools in their day.  They were not running fast enough, taking forever to debug, really hard to find problems.  Just on and on.  At that point statistical was coming up.  We had seen a lot of papers on that.  We asked if they want us to do statistical stuff.  They said that would be nice someday but what we really need right now is for what we are doing now to be much more effective.  We said okay.   We built the team in response to the customer requirement.  That is backwards from the way most EDA companies get built.  Most start with an algorithm or a technology and then say lets go find a problem.  We found a problem and then said lets go build a team.  We brought in Joao as the chief architect who was at IBM Yorktown and Cadence and has a PhD in distributed computing from University of New Castle.  At Chrysalis we had put together the first and second generation at Chrysalis.  We found really good people in other technology spaces.  We went and got some of the best and brightest out of Motorola Freescale, a guy who had developed a lot of the timing tools at Intel.  We recruited two very good academic advisors right from the gitgo: Duane Boring from MIT and David Blaau from
Michigan who really spent a lot of time with us.  They are not just show up for diner types.  They come here for days at a time.  Most of what we did was stay close to one of the largest IDMs that we had talked to during the summer.  We can not reveal the name yet but they design high speed digital components.  They have worked with us from the getgo on specs, giving us circuits, evaluating alpha and beta codes, and really stayed closely in the loop.  They are now putting it into production at 45 nm designs.  Really a company driven by the market, found the talent and then built the right product.

Here are some of the things we learned during the process.  Timing, the classic problem of timing and signal integrity.  Right up until the very end of the cycle people have tens of timing violations they can not get out of the system.  It has been very difficult for them to prioritize and fix those things.  Largely because things just take too long to run, literally 20 hour runtimes per corner for a signal integrity timing check.  That’s just takes too long.

The other key factor we heard while people talk about process variations and statistical this but statistical that, signal integrity, wires interfering with each other, is the primary killer of chips.  You have to look at that across lots of corners and lots of modes.  At the end of the day because of power constraints, you really have to make every path critical.  It is critical either for power or for timing. You bring everything right up to the edge.  The other thing we kept hearing loud and clear was if they change one wire or swap out one cell today, they have to do a 24 hour timing run.  That makes no sense.  The tool has to scale with the level of work that people are doing otherwise we will never get to the next generation of SoCs and big chips.



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-- Jack Horgan, EDACafe.com Contributing Editor.


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