March 25, 2002
EDA Week in Review
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dismissed dependent on the companies finalizing a settlement agreement and abiding by the terms of that agreement.
That's what I call cooperation in the spirit of fair competition. We need to see more of this in the industry.
In other news, Artisan Components, Inc. rolled out its SAGE-HSV High-Speed Standard Cell Library, which complements the SAGE-X Library with higher performance with minimal area increase, the company said.
downloading from Artisan's web site.
the time to volume production.
Artisan's SAGE-X Library for TSMC's 0.13-micron low-voltage process is the first result of Artisan's and Magma's ongoing collaboration, the companies said. In addition to completing the qualification of 0.25-, 0.18- and 0.13-micron cell libraries for use with Magma's IC implementation tools, the companies are creating a common data repository for easy access to updates and technical support. Subsequently, Artisan and Magma plan to jointly develop advanced methods of characterizing libraries to address other deep-sub micron effects.
In addition to the previous, Magma Design Automation formed "Fusion," a user group designed to serve Magma's worldwide users. The first formal Fusion meeting will be September 19-20, 2002 at the Westin Hotel in Santa Clara, Calif. The first call for papers will be issued in April 2002.
And Magma also announced the appointment of Pallab R. Chatterjee as the technical chair for organizing and convening the first Fusion conference. Chatterjee is currently president and managing partner of SiliconMap, LLC, a consulting services provider specializing in the creation of application-optimized multi-vendor tool flows and tactical tape-out engineering support. In addition to his participation in SiliconMap, he is the founder and partner coordinator of the EDA Integration Alliance Partners program, a collection of tool vendors and other partners working on mixed signal and memory interoperability solutions.
Model Technology announced ModelSim 5.6 with new features aimed at enhancing productivity and improving time-to-market, including up to 2X faster performance, new debug tools and an improved regression test flow.
ModelSim 5.6 offers up to 2X faster simulation performance, ensuring designers have the most powerful mixed-language simulation tool, Model Tech said. ModelSim 5.6 also includes a new option that allows designers to perform the elaboration step (design loading) once. This eliminates having to reload the design and SDF file for each simulation and is especially useful for regression testing and large gate-level simulations with timing files.
ModelSim 5.6 includes three new debug features that significantly increase productivity. First, a new data flow window, a visual tracing engine enables designers to quickly traverse forward and backward through a graphical view of the design to track problems. Second, ChaseX, a new x-tracing capability, automatically finds the source of any unknown while displaying the entire logical path. Third, an integrated C debugging capability lets a designer view C or C++ code directly in the ModelSim Source Window, greatly simplifying the debug of PLI, FLI or other C programs attached to a simulation. TestBuilder.net support
Synopsys Inc. released Formality 2002, its next-generation equivalence checker that addresses the need for an easy-to-use formal verification solution. Formality's new flow-based graphical user interface (GUI) guides the user through the equivalence checking process, reducing the time associated with setup and debug, the company said. A new simplified design read flow helps trim costly iterations in the equivalence checking process. Users can seamlessly import simulation scripts with the new simulation-style design read to ensure the right setup the first time.
According to Synopsys, the benefits of increased productivity and reduced risk of a silicon re-spin have made equivalence checking a mandatory component of today's verification. By matching the engineer's thought process, Formality 2002's new flow-based GUI provides immediate out-of-the-box productivity, it said.
In the company's news release, Fujitsu Digital Technology and NVIDIA both said they were using the tool.
This should be an interesting tool to watch as more and more leading edge design groups embrace formal verification techniques.
TransEDA PLC, joined the HyperTransport Technology Consortium. As its first deliverable as a Consortium member, the company will offer the new TransEDA HyperTransport Verification Suite consisting of a HyperTransport bus functional model (BFM) and a HyperTransport property library. The HyperTransport Technology Consortium is an active forum of companies developing advanced interconnect technology that is designed to greatly improve performance of a wide range of communications, storage and networking devices.
Celoxica Limited said it would unveil DK1.1, the next version of its Handel-C-to-hardware design suite at Programmable World 2002 on 17 April 2002. Scheduled for launch on 25 March 2002, DK1.1 includes a range of new features for reprogrammable system-on-a-chip design and will include support for the new Virtex-II Pro family of FPGAs from Xilinx Inc.
Sandwork Design Inc., a developer of transistor-level debugging tools, today announced that its waveform analysis tool, WaveView Analyzer, has been integrated with Nassda Corp's HSIM full-chip circuit verification and analysis software, and that Nassda will sell WaveView Analyzer directly to its customers under an OEM agreement.
Verplex Systems, Inc. expanded its Open Verification Library (OVL) to include support for the VHSIC Hardware Description Language (VHDL). The open-source library, originally designed for Verilog HDL-based designers, provides seamless interoperability between simulation and formal verification, eliminating the learning curve and accelerating the acceptance of formal design validation software. The library was designed using VHDL and works with any VHDL-based or mixed-language simulator.
Verplex donated its Verilog HDL-based Open Verification Language (OVL) library in 2001 to Accellera, the industry standards organization, to promote its use and encourage the library's acceptance as an industry standard. Plans for donating the VHDL version of OVL to Accellera for standardization will be announced shortly.
Verplex's BlackTie functional checker, a high capacity formal verification tool that accelerates the verification of system-on-a-chip (SOC) designs, currently offers full support for the Verilog HDL version of OVL. BlackTie support for the VHDL version of OVL will be announced later in the year.
The verification library can be downloaded at no charge from the Web Site located at:
and require the highest level of accuracy and capacity. Being able to accurately verify the timing, power, and functionality is essential for our success."
Mentor Graphics Corporation established a joint marketing agreement with Optimum Design Associates (ODA) to make the 2002 ODA Library for Expedition available for use with the Mentor Graphics Expedition Series of printed circuit board (PCB) design tools.
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-- Ann Steffora, EDACafe.com Contributing Editor.
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