April 15, 2002
EDA Week in Review
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Topping the news this week, Mentor Graphics Corp. reported that the U.S. District Court for the Northern District of California Court granted Mentor's motion for summary judgment of infringement against Cadence Design Systems Inc.'s (Quickturn) MercuryPlus products.
According to Mentor's news release, the Court found that the Cadence (Quickturn) MercuryPlus product infringed both claims of U.S. Patent No. 5,574,388 titled, "Emulation system having a scalable multi-level multi-stage programmable interconnect network" which were the subject of Mentor's motion. This order follows on the heels of the same Court's recent denial of a summary judgment motion brought by Cadence to dismiss the patent case for lack of standing, Mentor also said.
Synopsys, Inc. announced a new version of its physical synthesis tool, Physical Compiler 2002.02, which aims to provide designers with a timing closure flow that scales to twenty million plus gate designs. According to the company, there are three key capabilities introduced in this release of Physical Compiler that enable this high capacity flow: 64-bit platform support to more than double the practical capacity, Interface Logic Models, also supported by PrimeTime, to extend its hierarchical chip level capacity, and a new quick mode that offers a 5X runtime improvement in a design exploration flow.
Physical Compiler is also now available on the Solaris and HP 64-bit platforms. With 64-bit availability, Physical Compiler delivers the increased capacity needed by very large-scale system-on-chip (SoC) designs, Synopsys maintains.
Magma Design Automation, Inc. has teamed with Verplex Systems, Inc. to create a seamless flow between Magma's RTL-to-GDSII chip design system and the Verplex Conformal equivalence checker, including enabling direct control through Magma's GUI, the companies said. The enhanced integration is meant to streamline the process of incremental equivalency checking during the chip design flow. The companies said they have also agreed to jointly promote and reference the benefits of the combined flow for implementing multimillion-gate integrated circuits.
Magma and Verplex support industry-standard interfaces and data formats, therefore joint customers have already benefited from a well-integrated flow, the companies assert. To enhance the integration, the two companies will work together to add direct Verplex support into the Magma system environment. A menu option will be added to the Blast Fusion and Blast Chip GUI, allowing users to automatically invoke Verplex's Conformal directly from within a Magma session. The goal is a shorter the design cycle by making it faster and easier for chip designers to do incremental equivalency checking as desired throughout the implementation flow.
Also from Mentor Graphics comes a newly enhanced version of the company's LeonardoSpectrum synthesis tool, LeonardoSpectrum 2002a (LS 2002a). Mentor said the installed base of over 30,000 LeonardoSpectrum designers would benefit from enhanced operating system support, synthesis quality of results, device support and optimization features for Altera Corp., Actel, Lattice, QuickLogic, and Xilinx devices. The LS2002a enhancements are meant to enable designers to take full advantage of the newest and fastest FPGAs available, resulting in faster, lower cost end products.
Mentor also said LS 2002a has expanded its existing operating support to include the Microsoft Windows XP operating system, enabling users to take advantage of the latest high-speed personal computers available on the market.
and that it has been difficult finding an alternative solution that could offer the same performance to support verification of the company's designs.
Celestry Design Technologies, Inc. announced that three of its design tools have received qualification for Taiwan Semiconductor Manufacturing Company's (TSMC) 0.13-micron process. The qualified tools are: RelPro+ and RelXpert products for Hot Carrier Injection (HCI) effects, and the AnalogXpert product for device mismatch simulation analysis for TSMC's analog/mixed-signal (AMS) process technologies.
The company also reported shipment of the first member of its cell noise characterization family of products called CellXpert-CN, and that Socle Technology Corp. (Hsin-Chu, Taiwan), a TSMC Design Center Alliance company, has selected CellXpert-CN for cell noise characterization and Celestry's Nautilus-SI for signal integrity sign-off by Socle's RTL2Silicon service.
noise-clean design, the companies said.
performance of Xilinx FPGAs by using Synplicity's Amplify software.
The company also announced it has enhanced its Amplify Physical Optimizer software with a fully automated the Amplify physical synthesis flow, reportedly able to dramatically improve designer productivity and deliver performance improvements by up to 20 percent over logic synthesis alone. Synplicity said the automated flow initially supports the Xilinx Virtex, Virtex-E and Virtex-II devices, and Synplicity intends to support the Altera Stratix device family in a future release of the software. The enhanced Amplify software also offers support for Altera's APEX devices and Excalibur embedded processor solutions as well as the new Virtex-II Pro devices from Xilinx.
Driven by the proprietary Behavior Extracting Synthesis Technology (B.E.S.T.) algorithms, Synplicity said its Amplify Physical Optimizer software can synthesize even the largest programmable devices quickly and efficiently. The software also utilizes Synplicity's Total Optimization Physical Synthesis (TOPS) technology to perform simultaneous placement and logic optimization enabling designers to achieve maximum performance from their high-density programmable logic devices (PLDs).
Thirdly from Synplicity is an enhanced version of its PLD synthesis software, Synplify Pro which now includes support for the Verilog-2001 standard and support for new devices and operating systems. The latest version of the Synplify Pro software also includes several quality of results improvements and enhancements to its incremental timing engine and automated register re-timing feature, providing designers with added productivity and performance-improving benefits, the company said.
GoldenGate family of wireless/RF simulation tools the preferred choice with top chip and systems houses," Xpedion said.
An emerging technology seminar series titled, "Multi-Million Gate Chip: Mission Impossible? Think Again!" that outlines benefits of using a high-performance environment for complex system-on-chip (SOC) design, gets under way Thursday, April 18, in San Jose at the Doubletree Hotel. This seminar, sponsored by Get2Chip, Inc., Verplex Systems Inc., Plato Design Systems and Silicon Perspective (a company of Cadence Design Systems, Inc.) will also visit venues in Boston, San Diego, Denver and Austin. To learn more about the seminar series or participating companies, see
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-- Ann Steffora, EDACafe.com Contributing Editor.
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