April 22, 2002
EDA Week in Review
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Synopsys' Design Complier Gets Some Competition from Get2Chip's RTL Synthesis
Get2Chip Inc. rolled out its long-awaited RTL Compiler (a.k.a. G2C-RC), an RTL synthesis tool aimed at multi-million gate ICs. The company said it is optimized for designs larger than one million gates with aggressive clock speeds, and provides a "synthesis alternative for the SOC era," according to Get2Chip president and CEO Bernd Braune.
"G2C-RC is aimed at an under-served market needing consistent quality of results, super-fast runtimes, and confidence that new design tools will readily fit into existing flows and methodologies," Braune added. Get2Chips reports the tool has "seen more than 200 designs" and was built to be flow compatible current synthesis technology designers are familiar with. Procket Networks has converted its production flows to G2C-RC in the design of massive networking chip, Get2Chip reported.
To produce superior designs with less effort, Get2Chip said G2C-RC brings value-added features such as test insertion and power optimization. New analytic technologies built into the software include a global-based optimization engine enabling linear behavior over design and library size; constraint-directed logic, power and datapath optimization through total negative slack (TNS), that increases timing margins to optimize more than a design's critical path, providing extra timing margin for near timing critical signals.
Synopsys, Inc. launched OpenVera 2.0, backed by a number of supporting releases from partners.
New additions to OpenVera assertions (statements used to specify design behavior) are based on Intel's ForSpec language to combine the strengths of the OpenVera hardware verification language with Intel's newest formal verification language, ForSpec, Synopsys said. The end goal: to deliver a more comprehensive, open source hardware verification language to the verification community.
The combined technology enables OpenVera users to leverage next-generation functional verification methodologies by providing one common language for writing assertions and formal properties, Synopsys said. The addition of new assertions in OpenVera 2.0 marks a significant step forward in achieving OpenVera's objective of easing the verification bottleneck by enabling the development of a complete solution around an open, non-proprietary hardware verification language.
@HDL, Verplex Systems, Verilab Ltd., HCL Technologies and Novas Software, among others came out in support of OpenVera 2.0 with plans to expand their technology and introduce tools to support OpenVera assertions. OpenVera 2.0 may be accessed by downloading the Language Reference Manual (LRM) from the web site at http://www.open-vera.com. There are no licensing fees for OpenVera and access to the language and documentation is unrestricted, subject to the OpenVera license, Synopsys said.
Synopsys announced the availability of nine new OpenVera verification intellectual property offerings from Catalyst Program members ControlNet India, eInfochips, GDA Technology, HCL Technologies, Inspiration Technologies, Integnology, Nsys and Qualis Design.
Three additional companies have announced that they have integrated their products with Synopsys' VERA testbench solution to enhance verification productivity for OpenVera users. Forte Design Systems now supports VERA for its verification results analysis product, Perspective. Novas Software announced a tight integration between its Debussy knowledge-based debug system and VERA. Also, Verilab announced the integration of vzDoc with VERA to enable OpenVera users to quickly generate documentation from the testbench source code.
about a week in the Lake West Community of Dallas. Cadence sponsored this particular home, contributing $65,000 and organizing volunteers to build the house. The money was raised during last year's Stars & Strikes event, an annual Cadence bowling fundraiser that raised $1.6 million in 2001.
Warm fuzzies on the legal front: Altera Corp. and Cypress Semiconductor Corp. decided to settle the lawsuit brought by Cypress against Altera in June 2000 relating to Altera's acquisition of Right Track CAD Inc. The companies have agreed to release all claims against each other relating to Cypress' suit against Altera without any admission of liability. Terms of the settlement agreement were not released.
set of views and models supporting the leading EDA tools.
InTime Software, Inc. announced that Casey Jones joined the company as vice president of marketing, responsible for the company's corporate marketing operation. Jones' most recent experience was as vice president of marketing for Avant! Corp. Prior to Avant!, Jones was VP of Marketing for Integrated Silicon Systems (Research Triangle Park, NC) and co-founder and president of Performance Signal Integrity (Pittsburgh, PA). She holds B.A. and M.A. degrees from Stanford University, and an M.B.A. from Carnegie Mellon University.
Mentor Graphics Corp. completed the subsequent offering period relating to its cash tender offer for the publicly held shares of common stock of IKOS Systems, Inc. at a price of $11.00 per share. Mentor will acquire the remaining shares of IKOS common stock through a short-form merger in which all remaining IKOS stockholders who did not tender their shares in the tender offer will receive the same $11.00 per share in cash paid in the tender offer. Stockholders will receive information in the mail on how to receive payment for their shares. No vote or consent of IKOS stockholders is required for this merger.
Secondly, Mentor Graphics released HDL Designer Series tool suite version 2002.1 for design creation, analysis and management with productivity enhancements including an improved interconnect table that enables rapid creation of high-quality, well-structured hardware description language (HDL) for any level of design complexity, the company said. HDL Designer Series speeds the creation and analysis of complex ASICs, FPGAs and SoC designs, allowing teams to realize rapid time to market.
Interface-Based Design (IBD) simplifies interconnect creation problems by displaying design interconnect structures in an easy-to-view, compact tabular format that allows designers to rapidly specify signal connections and generate the equivalent VHDL or Verilog structural description, Mentor explained. The IBD description can also be viewed as a block diagram.
Thirdly, Mentor Graphics said that Ricoh has adopted its logic built-in-self-test (BIST) solution LBISTArchitect tool. By using the LBISTArchitect tool, Ricoh has developed a design flow for SoC logic that eliminates external stored patterns for increased test efficiency and enhances the overall quality of the design. Prior to using logic BIST, Ricoh established a BIST design flow for embedded memories using the Mentor Graphics MBISTArchitect tool, the companies said. In addition to using LBISTArchitect Ricoh also uses other Mentor solutions in their Design-for-Test (DFT) flow including the DFT-Advisor tool for scan insertion and the FastScan automatic test pattern generation tool.
Avant! Corp. announced that ATMOS Corp. selected its Star-SimXT simulation for full-chip analysis and verification of its SoC-RAM embedded memory macros that range in size from 1 Mbit to 64 Mbits. Star-SimXT, with its rapid timing and power verification, True-Hspice accuracy, and easy post-layout analyses with full back annotation, enables the high-quality production of customer-specified, compiled memory cells by ATMOS.
AccelChip, Inc. announced its first product, AccelFPGA, a high-level synthesis tool that links the Mathworks DSP design environment with industry standard FPGA design flows to dramatically reduce DSP design time by automatically creating synthesizable RTL models and simulation testbenches from the MATLAB technical design language and Simulink graphical design tool.
AccelFPGA is based on a research project conducted at Northwestern University from 1998 to 2001 under a grant from the United States Defense Advance Research Projects Agency (DARPA) entitled "MATCH: A MATLAB Compilation Environment for Adaptive Computing." AccelChip acquired exclusive rights to commercialize the MATCH technology when the company was founded in 2001 by Dr. Prith Banerjee, chairman of the Electrical and Computing Engineering Department at Northwestern University.
Headquartered in Schaumburg, Illinois, the company has developed the first commercially available EDA tool that directly reads MATLAB (.m files) and Simulink (.mdl files) designs and automatically produces synthesizable RTL models that are compatible with logic synthesis and simulation tools available from Synplicity, Synopsys, Mentor Graphics, Cadence Design Systems and others.
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-- Ann Steffora, EDACafe.com Contributing Editor.
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