May 20, 2005
EDA Week in Review
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May 13-17, 2002
Mentor Graphics Corp. received early termination of the waiting period required under the Hart-Scott-Rodino Act in connection with its previously announced proposed acquisition of Innoveda, Inc. Pursuant to an all cash tender offer, Mentor Graphics is offering to acquire Innoveda for $3.95 in cash per share of Innoveda common stock. Mentor Graphics' offer is scheduled to expire at 12:00 Midnight, New York City time on Tuesday, May 28, 2002, unless extended.
Synopsys, Inc. launched LEDA 3.1, a programmable coding and design guideline checker that features full-chip, mixed-language checking capabilities to speed development of complex system-on-chip (SoC) designs. LEDA 3.1 adds prepackaged rules that help designers maximize the performance of Synopsys tools such as VCS, Formality and Design Compiler, the company explained. LEDA 3.1 is meant to enable engineers to check their designs for compliance with reuse guidelines found in the Reuse Methodology Manual (RMM) and the DesignWare style guide. In addition, it provides enhanced programmability for creating custom coding guidelines.
HPL Technologies Inc. announced its new Design For Yield (DFY) division that focuses on the development of yield analysis and optimization software for integrated circuit (IC) designers. The Division's Design-For-Yield software enables customers to increase revenues and profits by creating semiconductor products that can be manufactured with more reliability and reach volume production sooner.
The new division is lead by VP and GM Mark Milligan, who joined HPL from Synopsys. Dr. Julie Segal, a noted researcher in the area of yield optimization manages the development group. Other members of the team have been involved in the development and marketing of some of the most technically advanced and successful design and test technologies in the industry while at companies such as IBM, Intel, and Cadence.
According to HPL, a number of challenges must be addressed for the industry to take advantage of the opportunity presented by deep submicron semiconductor processes, including increasing chip complexity and size combined with shrinking geometries that make devices more susceptible to systemic and random manufacturing defects; process variability must be accounted for in the design flow; lack of automated tools to measure yield-limiting factors for a design; little yield-related process characterization data available to designers; difficulty in creating high quality tests which meet PPM requirements, and length of time needed to diagnose defects.
HPL's said its Design-for-Yield tools have been applied on designs from semiconductor companies such as AMD, Cypress Semiconductor, Dominion Semiconductor, Fujitsu, Lucent, LSI Logic, National Semiconductor and Texas Instruments.
To meet interoperability requirements with existing design flows, the division participates in EDA, IP and semiconductor partner programs, such as those offered by industry leaders Synopsys and Virage Logic.
logic. Enhancements and tighter coupling of Verplex products to the transistor level enable next-generation design tool users to compare final LVS netlists to their RTL golden designs, helping them achieve functional closure faster and with more confidence. Verplex calls this new product flow Conformal Layout Versus RTL.
Monterey Design Systems released version 2.1 of Sonar, the company's physical prototyper. Monterey said Sonar is now the fastest and most accurate physical prototyper available on the market today, and enhances the interoperability of Sonar with leading implementation tools from other EDA vendors.
"By adding detailed gate-level placement capability in Sonar 2.1, we've made it possible for users of non-Monterey tools to apply the physical synthesis, prototyping, and early sign-off capabilities of Sonar within their existing design flows," said Wolfgang Helfricht, product marketing director at Monterey. "We've also further improved the speed of Sonar. On a flat five million gate customer design, Sonar 2.1 produced a physical prototype in under 5 hours -- this is five times faster than Sonar 2.0."
This release extends Sonar's capabilities beyond creating physical prototypes. By producing a fully placed, ready-to-route implementation, Sonar enables designers to hand off the design for final physical implementation with full confidence that it will meet all design requirements.
Verisity Ltd. is now shipping Specman Elite version 4, which features significantly improved performance, delivering about a 27 percent average speed improvement for compiled mode and about 15 percent for interpreted mode, enabling users to significantly shorten their verification whether using interpreted, compiled or mixed mode, the company said. In addition, Verisity said Specman Elite v4 provides enhanced functional coverage analysis, including integration with its SureCov code coverage tool and new usability features including a generation debugger that enables users to view all aspects of the generation process.
Mentor Graphics announced the VStation-30M emulator, the company's fifth-generation emulator and based on VirtualWires technology. The product will be marketed by the newly formed Mentor Emulation Division (MED), which will develop and market Mentor's emulation products worldwide, including all products from the recently acquired IKOS Systems.
For single-chip and multi-chip designs that require the highest capacity, Mentor said the VStation-30M provides up to 30-million usable ASIC gates at up to 2 MHz performance, at a lower cost per gate than previous generations. The VStation-30M provides 100 percent visibility of all signals at any time.
path from a HDL-based verification environment to an emulation environment, while providing performance of up to 20X over HDL simulators alone.
The VStation-30M emulator consists of nine array boards with Virtex XCV2000E parts. Physical dimensions have not changed from the previous IKOS emulator, the VStation-15M, at 36 inches in length, 21.5 inches wide, by 27.5 inches high. The small footprint allows the emulator to reside conveniently at the desktop or office. The VStation-30M emulator will be available in June 2002.
Cadence Design Systems, Inc. opened the Cadence High-speed Technology Centre in Shanghai. The new Centre will serve a growing customer base in Asia-Pacific with training, education programs, and methodology and consultancy services, with the objective being to increase the productivity of high-speed PCB companies and to develop the skills of designers and engineers by providing education as well as customized design solutions.
The Centre will use the Cadence SPECCTRAQuest Design and Analysis Environment as a standard platform to develop customized design flows and methodologies that will enhance productivity in customer-specific industrial applications. Technologies of importance in this market include high-speed buffer modeling, advanced simulation techniques, signal integrity, EMC and power delivery design and analysis, silicon-package-board interconnect design, and design kit development for regional integrated circuit suppliers.
In the initial stage, the Technology Centre will serve three markets: wireless communication, wired communication, and computing applications. The scope of service will expand to advanced packaging design and digital consumer applications over the next two years.
Beijing to train post-graduate-level engineers in electronic design.
Cadence's Lavi Lev sent an open letter to EDA company leaders to encourage participation in the OpenAccess Coalition:
Let's Be Open
An Open Letter to EDA Company Leaders:
We call on all leading EDA companies to support the creation of an
open, interoperable infrastructure among databases. We know that we
operate in a world of multiple databases: legacy databases from
Cadence, Synopsys, Avant!, and other EDA vendors, along with the
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-- Jack Horgan, EDACafe.com Contributing Editor.
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