July 08, 2002
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
The EDA Consortium's Market Statistics Service released 1Q2002 industry revenues of $962 million, compared to $989 million in 1Q2001. The industry has generated over $900 million in revenue for eight consecutive reporting quarters. Revenue growth in EDA Products and Maintenance and Semiconductor Intellectual Property was not enough to overcome decreases of over 40 percent in Services revenue, leading to an overall revenue decline in Q1. Total revenue as reported by the MSS decreased three percent in 1Q2002,compared with 1Q2001.
High growth rates were seen in specific EDA application areas, such as IC/ASIC Design Planning & Floorplanning Tools (80 percent growth over 1Q2001), Analysis Tools for IC/ASICs (58 percent growth), and Other IC Layout Tools and Reticle Enhancement Technology (RET, 34 percent growth). This growth indicates the need to immediately accommodate rapidly shrinking silicon geometries, noted Wally Rhines, chairman of EDAC and chairman and CEO of Mentor Graphics Corp.
For the full results, see
Synopsys, Inc. announced a full line of memory intellectual property (IP), which includes memory models, memory controllers, and memory BIST. The memory solution, as part of the DesignWare IP Library is available to designers through a single license and price, with no per-use fees or royalty payments.
The DesignWare IP Library provides a suite of memory IP designed to work together seamlessly in any design. The ability to use pre-designed, pre-verified IP blocks is key in enabling designers to dramatically reduce the time spent creating and verifying memory subsystems. The silicon-proven DesignWare memory solution ensures designers have access to the highest performance, easiest-to-integrate IP available.
The company said that the number of pre-verified memory simulation models in the DesignWare IP Library is constantly growing, with more than 10,000 models covering more than 25 memory vendors' devices available. The models integrate with simulators through the industry de facto standard SWIFT interface, which is supported by all Synopsys simulators and by all other major simulator vendors.
are ready for immediate use in the Magma flow. Dolphin Technology, Inc. is the first Magma partner to have a 0.13-micron library targeted to a leading foundry process.
5.2 million shares of HPL common stock, and assume all IDS employee stock options, which will convert into approximately 300,000 HPL stock options. HPL said this acquisition would expand its market reach, through complementary applications with a strong installed base that includes companies such as Analog Devices, Intel, LSI Logic, Motorola, NEC, OKI, Philips, Texas Instruments (TI), and Toshiba.
description in VHDL or Verilog. The IBD tabular format also enables design constraints and synthesis properties to be specified and then be propagated to the downstream phases of the design flow. Also, FPGA Advantage's debugging capabilities have been expanded with version 5.3 to include visualization of text files during interactive simulation debug. These graphical and tabular diagrams of HDL source code enhance HDL simulation and improve design verification productivity.
Mentor Graphics also reported that Faraday Technology Corp. has selected its Design-for-Test (DFT) tools for its SoC design flows. Faraday said it selected Mentor Graphics for its proven DFT technology and ability to improve productivity and test quality and reduce test cost. Faraday also said it would use the FastScan tool for automatic test pattern generation and the MBISTArchitect tool for memory built-in self-test. Faraday also bought the BSDArchitect tool for automated boundary scan implementation, the DFTAdvisor tool for scan synthesis and testability analysis and the DFTInsight tool for graphical DFT debug and analysis.
Zenasis Technologies, Inc. closed its second round of funding with an investment from WestBridge Capital Partners. The additional second round investment by WestBridge Capital brings the total amount raised to $10 million since Zenasis was founded in 2000. Funds will be used as working capital to expand Zenasis' research and development efforts. Sigma Partners led its second round of funding in March 2002, followed by Selby Ventures and VentureTech Alliance.
MontaVista Software, Inc. and Xilinx, Inc. announced that MontaVista Linux Professional Edition would support the Xilinx Virtex-II Pro FPGA, which enables developers of embedded Linux products to target a completely programmable, re-programmable and field-upgradeable system platform. The collaboration allows the broad base of Linux developers to accelerate their embedded designs with the ability to reconfigure, enhance and optimize those designs throughout the entire product development life cycle. This announcement represents the first time FPGA-based systems developers can build and deploy on a Linux platform.
The integration of the Virtex-II Pro hardware platform with embedded Linux yields a flexible design environment, in which engineers can lower product costs and accelerate their time to market. Consequently, developers will benefit from the advantages of open source software to lower their product costs on a single, company-standard hardware platform that can target many different applications. This facilitates a quick start to design projects and supports fixes, enhancements and performance optimization to hardware or software throughout the entire product development process.
Xilinx has joined the MontaVista Partnering program, which gives users access to a world-class group of hardware and software providers who have embraced MontaVista Linux. With a wide variety of partners from which to choose, the program is dedicated to offering solutions to customer challenges. MontaVista has also joined Xilinx's Alliance program of industry partners, providing a full eco-system of support, including EDA, IP cores, design service, reference design and embedded solutions for the Virtex-II Pro.
@HDL announced that Toshiba Corp. has selected @HDL software for use on upcoming chip development projects. Toshiba said it selected the @Designer graphical debugging and design analysis product from @HDL after an extensive evaluation. Toshiba semiconductor engineers developing large-scale SoC designs will use the @Designer tool, the companies said.
Celestry Design Technologies, Inc. rolled out a universal model, AgeMOS, for accurate reliability modeling during deep-sub micron CMOS circuit simulation. Celestry is also announcing tools and services that support model development and reliability modeling options for its transistor-level circuit simulators. AgeMOS models enable the flexibility of incorporating new degradation mechanisms for transistor degradation analysis into a circuit simulation, and are more accurate than previous generations of reliability models. They work with popular transistor-level circuit simulators, like Celestry's UltraSim, a multi-million-transistor simulator.
integrate Improv's configurable DSP technology and methodology; a suite of application software; SOC integration and extension capabilities, including ARM/MIPS interfaces; a full SOC verification environment and tool suite; and a reference platform.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Ann Steffora, EDACafe.com Contributing Editor.
Be the first to review this article