July 15, 2002
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

EDA Veteran Paul Lippe Returns as President and CEO of InTime Software;

NASDAQ Halts Trading of HPLA, Chairman and CEO MIA

Topping the news this week was the appointment of Paul Lippe to president and CEO of InTime Software, Inc. Lippe was formerly senior vice president of business and market development at Synopsys, Inc. After departing from Synopsys in October 1999, Lippe served as CEO of SKOLAR, spun out of Stanford Medical School that developed e-learning and digital library technology.
Lippe said coming back to EDA after delving into the Internet realm gave him a "re-recognition of the fundamental value of EDA. It's key technology to drive a whole society forward," he explained.
In other news, this on the not-so-pleasant side, the Nasdaq Stock Market halted trading of silicon infrastructure player HPL Technologies, Inc. for "additional information requested." The company has since blamed the mishap on its former chairman and CEO David Lepejian who cannot be located, the company reported. Nasdaq said trading in the security would remain halted until the company has fully satisfied its request. Earlier, HPL Technologies did report that it began investigating certain accounting irregularities involving revenue reported during prior periods, removed Lepejian. Based on a preliminary investigation, the company said it appears that a material amount of revenue was
improperly recognized during one or more earlier periods from sales to an international distributor.
Positive news did come out of the silicon infrastructure space, with PDF Solutions, Inc.'s announcement that it has expanded its yield simulation and analysis capabilities in Yield Ramp Simulator (YRS) 3.0 software, to be released in August. The new version of the company's software strengthens its proprietary approach to predict, analyze, and improve yield of ICs, the company said.
YRS software is a yield modeling and analysis tool that evaluates the impact of specific IC design attributes and manufacturing process variations. Version 3.0 offers an order of magnitude throughput improvement, increasing the amount of data that can be analyzed accurately in the same time period, PDF said. The latest version also provides a more flexible design attribute extraction engine, which enables fast and accurate analysis of process-design interactions, especially suited for today's largest, most complex designs, the company explained. The new features of the software continue PDF's strategy toward Design-Based Yield Improvement technology.
LogicVision, Inc. formed an engineering support and services division for engineering and consulting services for chip, board and system level design-for-test (DFT). In addition, LogicVision appointed Kenji Baba to vice president of the new division. Baba is chartered with the management and expansion of the division's focus on supporting customers' seamless implementation of Embedded Test from chip design through to systems development.
LogicVision believes the new division will provide its customers with additional LogicVision resource to help shorten implementation time, as well as foster seamless hand-off of chip design integration to manufacturing test. The engineering and consulting services will play a vital role not only in enabling the accessibility of LogicVision's proven Embedded Test Solution, but also in optimizing for future chip design and manufacturing applications, the company said.
LogicVision said it's engineering service and support division will focus on five major activities that include: (1) test architecture consulting services; (2) turnkey DFT services; (3) test program generation; (4) debug and test services; and (5) worldwide applications engineering support.
LogicVision also announced that Trebia Networks, Inc. successfully implemented LogicVision's Embedded Test Solution for silicon debug in its prototype storage networking chip. Based on this experience, Trebia said it plans to leverage LogicVision's Embedded Test technology for its follow-on chip scheduled for production. With the prototype chip, Trebia said it has already seen dramatic improvements over traditional test methods as measured by reduced time-to-debug (from hours to weeks) and reduced cost.
LogicVision's Embedded Test technology was applied on Trebia's 0.18-micron prototype chip to isolate initial test program issues. Trebia ran multiple tests on its device in a lab setup environment within minutes, the companies reported.
Thirdly from LogicVision, the company said that Teradyne production testers Catalyst and Tiger are certified by LogicVision to be Embedded Test Ready, which means they are able to access LogicVision's Embedded Test Solution. This integration is a result of a continued partnership between the two companies, and provides mutual customers with an optimized test solution designed to speed time-to-volume production and reduce total cost of test, the companies said.
Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp. revealed that the code/lab Embedded Developer Suite for MIPS-based processors is now available. This code/lab release supports the MIPS architectures and MIPS-based processors developed by MIPS Technologies' licensees such as IDT, NEC Corporation and QuickLogic. The addition of code/lab broadens the Accelerated Technology Real-Time Operating System (RTOS) offering to developers building high-performance, low-power system-on-a-chip (SOC) applications.
Cadence Design Systems, Inc. said that Sean M. Maloney, executive vice president of Intel Corp. and general manager of the Intel Communications Group, has been elected to the Cadence Board of Directors. Maloney, an Intel employee since 1982, has held a number of technical, managerial and executive posts in Europe, Asia and the United States. He is also a member of the Board of the US/China Business Council.
Synopsys, Inc. has hired intellectual property (IP) expert Pierre Bricaud as director of research and development for its Intellectual Property and Systems business unit. His responsibilities include driving the company's growing IP business in Europe and working closely with European customers to ensure that Synopsys' IP solutions solve their design challenges. Bricaud comes to Synopsys from Mentor Graphics where he started Mentor's IP Factory in Sophia Antipolis, France in 1997. Later he became responsible for SoC European strategic relationships. He holds an engineering degree from the Institut Superieur d'Electronique de Paris (ISEP) with a major in computer science.
Additionally, Bricaud and Michael Keating, vice president of engineering of Synopsys' IP and Systems business unit, recently published the third edition of Reuse Methodology Manual for System-On-A-Chip Designs, available from Kluwer Academic Publishers.
Open Core Protocol International Partnership (OCP-IP) announced that Mentor Graphics' Inventra IP Division has joined the organization. Membership in OCP-IP enables Mentor to provide its customers better design reuse and faster time-to-market by ensuring the rapid creation of interoperable virtual components.
Virtual Silicon Technology, Inc. received an order from 1st Silicon, Malaysia's largest wafer foundry, to port its SIP to 1st Silicon's 0.18-micron process technology. The agreement covers Virtual Silicon's standard cell library as well as two I/O pad libraries.
Q Design Automation announced that Artisan Components has completed an agreement to license Q Design's Qtrek-Migrate IC layout optimization software. Artisan said it would use the software as part of its automated flow to migrate standard-cells, memories, and memory compiler products to next generation processes.
Sunplus of Taiwan said it has deployed Conformal Logic Equivalence Checker (LEC) from Verplex Systems, Inc. throughout its IC design flow. In addition, Sunplus said it is using Conformal LEC as its final standard sign-off criteria for all of its chip designs.

Altera Corp. said the U.S. District Court for the Northern District of California issued a preliminary injunction enjoining Clear Logic, Inc. and its distributors from selling semiconductor devices made, designed, configured or programmed through or with the aid of Max+PlusII software-generated bitstream files. Altera also said the court ordered Clear Logic to destroy all semiconductor devices in their possession that were programmed with the output of Altera's software tools.
Clear Logic had previously disputed Altera's contentions. Clear Logic filed for bankruptcy protection under Chapter 11 of U.S. bankruptcy law in January 2002. The company's filing was prompted, in large part, by the pending Altera litigation. Altera sued Clear Logic in November 1999, alleging interference with customer relations and unlawful appropriation of registered mask work technology. In October 2001, the court issued several rulings including a finding that as a matter of law using the bit stream from Max+PlusII to program Clear Logic devices violates Altera's software license.
Altera released version 2.1 of the Quartus II design software, featuring a new timing closure methodology based on ASIC design techniques that can significantly accelerate the process of meeting timing requirements in multi-million gate system-on-a-programmable-chip (SOPC) designs. Altera said it is the first programmable logic supplier to deliver a methodology for timing closure as an integrated part of its existing tool suite. One of the significant new features of Quartus II version 2.1 is the new SignalTap II embedded logic analyzer. Altera said its SignalTap II is a second-generation system-level debug tool that captures and displays real-time signal
behavior in SOPC designs.
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-- Ann Steffora, EDACafe.com Contributing Editor.

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