August 19, 2002
EDA Week In Review
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Mentor Graphics Assists Out of Work Design Engineers
offered to qualified candidates in all North American Mentor Graphics training locations, including Austin, Boston, Chicago, Dallas, Denver, Minneapolis, Portland and San Jose. A complete list of course descriptions, schedules and training locations is available at
http://www.mentor.com/es. For more information and to apply for the Displaced Worker Program please visit
remaining issues in this case, including Mentor's claim of trade secrets theft, is set for January 6, 2003. Prior to the present summary judgment ruling on the '725 patent, the court invalidated another single claim in the patent.
Speaking of Cadence Design Systems, Inc., the company and Datang Mobile Communications Equipment Co. Ltd. announced a collaborative effort to develop standards-based solutions that is aimed at helping 3G developers in China and the rest of the world accelerate time to market for mobile communications products. The first solution resulting from this collaboration is a base-band library, which fuses Datang's uplink and downlink simulation models with the Cadence Signal Processing Worksystem (SPW). For details, see
Cadence also unveiled a joint initiative meant to help customers facilitate the smooth transition to fabrication through physical design verification using Cadence's nanometer design technology. Under this initiative, Cadence Assura physical verification solution DRC decks for 0.25-, 0.18- and 0.13-micron CMOS logic technologies are now available for download free-of-charge on UMC's “My UMC” customer website. This easy access to high-quality, foundry-level, silicon-proven rule decks should save customer time and resources, thus enabling them to remain focused on their nanometer chip designs.
Synopsys, Inc. reported that the waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976 with respect to Synopsys' pending tender offer for all outstanding shares of inSilicon Corp. expired without a formal request from the Federal Trade Commission for additional information or documentary material. The parties have previously received clearance from the German Federal Cartel Office to complete the acquisition and plan to file a pre-merger notification in Taiwan. Synopsys' completion of its tender offer for inSilicon shares remains subject to certain conditions, including the tender of a majority of the outstanding shares of inSilicon.
Mentor Graphics also announced DMS2002, the latest version of its design data management infrastructure solution that consolidates and manages work-in-progress design data and provides a tight integration between the design engineer and the extended enterprise. According to the company, DMS2002 expands the accessibility of component information from the corporate library to the wealth of data available on the Internet through specialized content providers, giving users a broader portfolio of decision and selection criteria in a very early phase of the design process.
DMS2002 now includes DMS-Xchange, a new communication and interchange platform that provides a dedicated eXtensible Markup Language (XML) link to third-party content providers. The first of several DMS-Xchange offerings is DMS-Xchange for PartMiner, which is the result of an agreement between Mentor Graphics and PartMiner, Inc., a supplier of electronic component information services to the electronics industry. DMS-Xchange for PartMiner allows DMS2002 users with PartMiner subscriptions to incorporate PartMiner component data into their company's library as Computer-Aided Engineering (CAE) symbols and component information.
to create textual representations of digital designs. The training software provides a unique learning environment, designed to provide value to each individual user's needs and skill levels. The Verilog CBT includes training software, quizzes, projects, language reference manuals, software manuals, and language and software tutorials. In addition to ModelSim and LeonardoSpectrum, also included in Verilog CBT is the web edition of Altera's Quartus II design software, used for advanced PLD and SoC designs.
Verilog CBT was created by Dr. Zainalabedin Navabi, expert and author of several publications related to Verilog, including, Verilog Digital System Design, and VHDL: Analysis and Modeling of Digital Systems. Dr. Zainalabedin Navabi is an associate professor of electrical and computer engineering at Northeastern University. He holds doctorate and master's degrees in electrical engineering from the University of Arizona and a bachelor's degree in electrical engineering from the University of Texas at Austin. Navabi has authored several books and technical papers on Verilog and VHDL, including VHDL: Analysis and Modeling of Digital Systems, currently in its second edition.
Verilog CBT is available now and carries a list price of $199.95 and is available from McGraw-Hill at www.books.mcgraw-hill.com, amazon.com and other online retailers.
key design issues such as verification and Intellectual Property (IP) modeling and integration. The addition of the Chief Strategy Officer comes as the momentum grows towards designing at higher levels of abstraction to meet chip complexity requirements and as the need grows for standardization of a system level-modeling platform that benefits the entire electronics industry.
Newly elected officers of OSCI for 2002-2003 also include: Chairman and Treasurer: Stan Krolikoski, Cadence Design Systems, Inc.; Vice Chairman: Takashi Hasegawa, Fujitsu Limited; President: Kevin Kranen, Synopsys, Inc.; Secretary: Janice Benzel, Motorola, Inc.; Chief Strategy Officer: Guido Arnout, CoWare, Inc. In addition to the above-mentioned companies, other companies represented on the OSCI Board of Directors include ARM Ltd., Mentor Graphics, and NEC.
products. Tower's new Fab 2 facility, currently prototyping 0.18 um micron products, is expected to begin volume production by year-end 2002. The facility will produce up to 33,000 200 mm wafers per month, the companies reported.
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-- Ann Steffora, EDACafe.com Contributing Editor.
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