September 22, 2002
Welcome to the first issue of EDA Weekly
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
application cost and power.
The DesignWare BlueIQ Core provides both VHDL and Verilog RTL source code for the baseband, as well as C-language source code for the link manager firmware that can reside in RAM, ROM, or Flash memory. A verification environment is also included for bus functional models and test suites. The BlueIQ Core connects to the host CPU via a standard UART interface and is compatible with any qualified Bluetooth high-level stack and application profiles. The BlueIQ Core is optimized to connect directly to the Silicon Wave SiW1701 radio modem and can be connected with other radio modems on request.
A DesignWare Bluetooth Development Kit is also available, which consists of a silicon implementation of the BlueIQ Core, a Silicon Wave SiW1701 radio modem chip, and a demonstration version of Bluetooth software from Mezoe. Synopsys worked closely with two Bluetooth industry leaders Silicon Wave and Mezoe on this product.
Cadence Design Systems, Inc. unveiled its
Cadence Encounter RTL-to-GDSII architecture for nanometer-scale digital design implementation that combines silicon virtual prototyping and detailed IC implementation into a unified architecture with a single in-memory data model and user interface. Cadence said all SoC Encounter customers will be upgraded to version 2.2, which is based on the new architecture and nanometer technologies, including the NanoRoute graph-based routing engine and CeltIC signal integrity analyzer.
the highest priority portions of the design, and to make systematic, predictable progress toward tapeout.
Monterey Design Systems reported that its IC Wizard hierarchical design planner enabled the Telecommunication Network Systems Group of Fujitsu Limited to achieve a 15 percent reduction in die size on a 3.3 million gate telecommunications chip, which contains 3.3 million logic gates, 313 RAM macros, more than 10 clock domains and was fabbed on a six-metal-layer, 0.18 µm process technology.
recent 5.0 release of the Cadence CIC software. Customers moving to the Cadence CIC 5.0 release will be able to continue using Synchronicity for design collaboration and management. Synchronicity support for Cadence CIC 5.0 is available to select customers now and will be universally available in October.
using the Magma integrated approach.
Magma also reported new senior management appointments to its executive staff. Saeid Ghafouri has been named senior vice president of field operations and Venktesh Shukla has been named senior vice president of marketing and business development. Both report to Roy E. Jewell, Magma president and chief operating officer.
electronics engineering in India.
an AE, then building the field AE organization, and finally was given responsibility to rebuild the factory support infrastructure, including corporate AEs, educational services and documentation. Ghafouri began his career as an IC designer for Data General. He has a bachelor's degree in electronics engineering.
Synopsys Professional Services assisted ARC International with two strategic projects that enable ARC and its customers to integrate ARCtangent microprocessor cores more quickly and reliably into SoCs at 0.13-micron and below geometries. In addition, ARC has now joined other premier IP providers as a member of the Synopsys Professional Services Alliance Program. The Alliance Program offers developers of complex ICs a comprehensive set of design services leveraging design solutions from best-in-class technology vendors, enabling customers to gain access to complete product development solutions that shorten product development time.
In the first project with ARC, an integration flow from RTL to Placed Gates was established, providing a faster and more predictable route for implementing designs utilizing ARC's configurable processor cores on various silicon technologies. In the second project, Synopsys design consultants helped develop a VERA and C-based verification environment for ARC's configurable processors and its peripherals. ARC uses this environment for internal validation of their cores, as well as by the company's customers to ensure correct integration of ARC IP into their SoC designs.
Synopsys also announced the latest addition to its TetraMAX ATPG family, TetraMAX TenX, which provides distributed processing for automatic test pattern generation (ATPG). Distributing compute-intensive ATPG tasks across multiple CPUs, workstations and servers helps accelerate ATPG for the largest and most complex designs, thereby reducing manufacturing test development time and lowering the overall cost of test, the company said.
Parthus Technologies Plc and 1st Silicon (Malaysia) Sdn. Bhd. have announced a licensing agreement meant to enable SoC designers to access essential Parthus phase lock loop (PLL) IP from 1st Silicon as part of the company's foundry service. As the first phase of the agreement, 1st Silicon will verify the Parthus PLL IP in silicon using a test chip containing multiple PLL instantiations designed to exercise the extremes of the design range. Further verification will be completed through simulations using an automated test bench designed to test all valid PLL configurations in 1st Silicon's 0.25-and 0.18-micron CMOS process technologies.
Alatek, Inc. introduced a new three million ASIC gate design emulator at $99,600 “Permanent License Purchase,” which is a fraction of what other EDA vendors require for similar capacity and performance products, the company said. The product, COMULATOR 3M, is based on a new release of Alatek's proprietary hardware embedded simulation (HES) technology.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Ann Steffora, EDACafe.com Contributing Editor.
Be the first to review this article