October 07, 2002
Mentor supports next-gen GDSII format, Synopsys enters Logic BIST market
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Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Topping the news this week was Mentor Graphics Corporation's announcement that it would support the still-unnamed GDSII replacement format. The new format will be supported in Mentor's Calibre and IC Station tools as early as 1Q03. This new database format is a replacement to GDSII, which has been used in the industry to transfer physical design data for decades. This next-generation, non-proprietary, interchange file format will be first used for leading-edge technology nodes, such as 130nm, 90nm and 65nm and features improvements such as data volume efficiency
Mentor Graphics said it has been responsible for the editing of the specification, the initial specification itself (Version 3 SLF), and assigned some of its employees, including one of its top software engineers, Laurence Grodd, as technical editor, and several other individuals as liaisons to the SEMI NSF WG (SEMI New Stream Format Working Group). Mentor agreed to hand off all proprietary rights to Version 3 SLF and any subsequent versions that include numerous contributions from Working Group members from other EDA companies, semiconductor companies and the mask industry. Mentor said it also contributed a GDSII-to-SLF translator to Working Group members on four platforms, as well as
participated in both the Working Group and SEMI Data Path Task Force.
Product News
Synopsys, Inc. entered the logic BIST market with DFT Compiler SoCBIST, which the company said offers deterministic logic BIST capabilities. Compared to full scan, SoCBIST is meant to provide test cost savings by reducing test time and data volume, while deterministically retaining scan's high fault coverage, Synopsys maintained, and said the tool is integrated within its physical synthesis flows. Synopsys also said the SoCBIST tool reduces tester time by more than 10 times and reduces data volume by 100 to 400 times compared to traditional scan. Additionally, SoCBIST needs 20 or fewer ATE pins and less than one percent of the vector memory required by a full scan approach.
A bi-directional link between Inovys Corporation's Ocelot automatic test equipment (ATE) and Synopsys, Inc.'s TetraMAX ATPG. The link is based on the IEEE standard 1450 Standard Test Interface Language (STIL) and enables direct transfer of ATPG patterns to the ATE for manufacturing test and for direct transfer of device failure data from the ATE back to TetraMAX ATPG for failure diagnostics. According to the companies, by using this linked ATPG-ATE solution, designers can pinpoint and analyze defects quickly, enabling them to achieve faster time to volume with higher yields of their complex SoC designs.

Teseda Corporation unveiled its Validator 500, what the company claims to be the world's first design-for-test (DFT)-focused validation system. The Validator 500 is a laptop-sized, affordable test system, the company explained, which is meant to enable design and product engineers to rapidly validate DFT tests for prototype ICs and to quickly test engineering-sample devices, cutting the time to volume production.

Teseda said it developed the Validator 500 with DFT-Intelligent software that imports not only test patterns but also the structural information about the chip's DFT. This allows the Validator 500 to provide data views that link the design and test information, and reduce the time required to validate DFT tests.

The Validator 500 DFT-Optimized hardware was designed with the requirements necessary for exercising DFT structures, which resulted in a completely different architecture than traditional testers and significantly reduced the cost and size of the system, Teseda added.

Monterey Design Systems' entire product line is now available on the Linux operating system for Intel and AMD processors aimed at chip designers performing their own in-house physical design using a customer-owned tooling (COT) flow.

TNI-Valiosys, a French provider of system-design solutions for embedded and real-time applications, announced a new release of CosiMate, a co-simulation tool for system-level mechatronics simulations providing access to engineers who want to simulate their heterogeneous models at system-level. In contrast to a point-to-point solution, where a simulator is programmed to uniquely dialogue with another simulator, TNI-Valiosys' CosiMate uses an open architecture based on a co-simulation bus. This solution offers two major advantages: an open architecture enabling multipoint integration and communication of heterogeneous simulators, and the ability to simulate models across the network
optimizing CPU usage and simulation performance, the company explained.
Tensilica, Inc. has licensed IBM's CoreConnect on-chip bus architecture. Tensilica also announced the availability of an Xtensa-to-CoreConnect bus bridge in the fourth quarter of 2002. The bridge interfaces Tensilica's configurable Xtensa processor to the IBM CoreConnect bus so customers can quickly merge multiple Xtensa processors to CoreConnect-based SOC designs.

Corporate Appointments

Mentor Graphics appointed Marc A. Corbacho to VP of sales for the Americas. Based in Mentor's sales office in Waltham, Mass., Corbacho has over 20 years of sales and marketing experience with software, semiconductors and optical solutions. Most recently he was the VP of sales and marketing for NetOctave, a developer of silicon-based network security solutions. Prior to that, he was the director of North America sales, geographic and key accounts for Lucent Micro Electronics, and has held sales and management positions with VLSI and Motorola SPS. Corbacho holds a bachelor's degree in Electrical Engineering from the University of New Mexico and has
completed the Harvard Business School Program for Management Development.

Artisan Components, Inc. appointed James Hogan to the newly created position of senior VP of business development. Hogan brings to Artisan more than 28 years of experience in the semiconductor design and manufacturing industry. He has held senior engineering, marketing and operational management positions at Cadence Design Systems, Inc., National Semiconductor Corporation and Phillips Semiconductor. Most recently, he served as senior VP of business development and the senior member of the Office of Chief Technologist at Cadence Design Systems. Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A all from San Jose State
Analog Design Automation, Inc. appointed Martin G. Harding to VP of worldwide field operations, reporting to CEO and president Matthew Raggett. Also, Geoffrey Rodgers has been named as director of western region sales. Rodgers, who will report to Harding, was recently director of sales with Plato Design Systems prior to its acquisition by Cadence.
AccelChip, Inc. appointed Michael Bohm to Chief Technical Officer where he will oversee all product and technology development. Bohm was most recently Chief Scientist and Technology Fellow for Mentor Graphics. Prior to AccelChip and Mentor Graphics, Bohm was an IC design manager at Harris Semiconductor where he worked closely with the founders of Synopsys when they started their company in Research Triangle Park, North Carolina. Bohm worked onsite at Synopsys as a Harris Semiconductor employee from 1989 to 1991 where he contributed to the development of their Design Compiler technology. Bohm joined Mentor Graphics in 1991 and led the development of
AutoLogic II, and later became VP of Engineering at Exemplar. When Mentor Graphics folded Exemplar into the company, Bohm oversaw the technical development and direction of their HDL tool set for FPGA design. Bohm holds a B.S. Electrical Engineering degree from the Florida Institute of Technology.

Customer Endorsements

Mentor Graphics announced that STMicroelectronics (ST) would deploy the Calibre Interactive tool for physical verification of cell and block designs. This development represents ST's expansion of Calibre technology throughout the design flow, from cell/block and full-chip verification through manufacturability. Calibre has long been the internal standard for full-chip designs at ST, the companies reported. By moving forward with Calibre Interactive, ST will enjoy full support of golden reference Calibre rule files for cell/block designs. Calibre seamlessly integrates with the existing layout environment at ST, giving designers an interactive version of Calibre.
Exar Corp. said by using Sequence Design's Columbus-RF parasitic extraction software for mixed-signal and digital circuits, the company has seen faster time-to-market and improvement of critical timing analysis.
Exar said it has employed Columbus-RF on a number of sophisticated designs over the past two years, ranging from a 0.18-micron to 0.35-micron for its networking IC designs. Another benefit the company reported was the ability to integrate the Sequence tools quickly. It took using only a two-page description of Columbus-RF, and a couple of questions, for Exar to be off and running, it said.
Incentia Design Systems, Inc. announced that Divio Inc. has taped out a design and improved the timing on its critical path using results from using Incentia's DesignCraft Pro physical synthesis software. In addition, Divio said it uses Incentia's static timing analyzer, TimeCraft, in its digital video design flow.

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-- Ann Steffora, EDACafe.com Contributing Editor.


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