October 21, 2002
Verisity Adds 16 Universities to its Academic Partnership Program
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Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Verisity Ltd. expanded its University Program with 16 new universities joining in less than a year, which brings the number of participating academic institutions to 27. The program was started in December 2001 with eleven charter members, and it enables students to gain valuable experience with best-in-class verification solutions, and to better prepare the next generation of verification engineers for real-world experiences. As functional verification becomes an increasingly critical part of the overall design process, Verisity's University Program is supplying universities with the latest in market-proven technology, the company said.

The 16 new program members are:
Bournemouth University, Poole, England;
Concordia University, Quebec, Canada;
De Montfort University, Leicester, England;
Faculty of Electrical Engineering and Computing, Zagreb, Croatia;
George Mason University, Fairfax, Virginia;
Michigan State University, East Lansing, Michigan;
North Carolina State University, Raleigh, North Carolina;
Pennsylvania State University, University Park, Pennsylvania;
Polytechnic University, Brooklyn, New York;
Politecnico di Torino, Torino, Italy;
State University of New York at New Paltz, New York;
Syracuse University, Syracuse, New York;
Transilvania University, Brasov, Romania;
University of Bristol, Bristol, England;
University of Pittsburgh, Pittsburgh, Pennsylvania;
Washington University, St. Louis, Missouri.

For more information regarding the University Program and a complete listing of participating universities, please go to:

In other corporate news,
Emulation and Verification Engineering (EVE), SA joined the Model Technology Value Added Partnership (VAP) program to validate the integration of ZeBu, its emulation platform, with Modelsim, the VHDL and mixed-language simulator.

Synopsys, Inc. and
Open Core Protocol International Partnership (OCP-IP), the association providing a common, open source standard for intellectual property core interfaces, announced the development of a SystemC modeling methodology for OCP-based SoCs.
Nokia, Texas Instruments, Sonics and Synopsys said they would publish an application programming interface (API) specification and example models to enable OCP users to utilize SystemC design and verification methodologies and create SystemC models for OCP-compliant components.

The new methodology covers generic modeling of communication with hardware and software components down to cycle-accurate OCP modeling at the transaction level. OCP-IP members Nokia, TI and Sonics, together with Synopsys, are jointly writing the OCP SystemC API specification. The API specification comes with SystemC examples, comparable to the widely accepted 'simple_bus' model Synopsys contributed to the Open SystemC Initiative (OSCI) earlier this year. A white paper is available from the OCP-IP Web site today at
http://www.OCPIP.org. The API specification and SystemC example models will be available for download from the contributions area on the OSCI web site in Q4 2002.

ReShape, Inc. joined ATAP, the
ARM technology access program. With this agreement, ARM said ReShape is qualified to provide physical design services to ARM's Silicon Partners as well as system companies embedding ARM CPUs in electronic products, especially those in the high-demand, high-growth wireless, graphics, multimedia and networking markets. There are currently 34 Partners in the ATAP program, with more than 3,200 engineers available to work on ARM core-based SoC designs. ATAP design Partners must go through a strict qualification process to become an ARM Approved Design Center. For more information on the ATAP program, please email info@arm.com or visit the ARM web site.

Product News

Topping the product news,
Synopsys added noise modeling capabilities to its Liberty open library standard. The new capabilities should allow library suppliers and developers using this format to make their cell libraries ready for a comprehensive signal integrity flow for 130 nanometer (nm) designs and below, the company said. STMicroelectronics' Research and Development worked with Synopsys to develop the noise modeling solution within the Liberty standard that closely mirrors noise effects being seen in 90 nanometer silicon. Synopsys also collaborated with library provider Artisan Components to extend Liberty's modeling foundation to enable timing and signal integrity closure.

Synopsys also announced the availability of its Switching Activity Interchange Format (SAIF) as an open source format and the release of an open source parser for the OpenVera hardware verification language. Synopsys said it is highlighting these advancements at the tenth semiannual Synopsys EDA Interoperability Developers' Forum held in Sunnyvale, California.

SAIF provides switching activity information to power optimization and analysis tools. By standardizing SAIF as an open source format, Synopsys is helping to streamline the design flow with the availability of a compact, proven format for simulators to capture the switching activity information needed by downstream power and reliability tools. Through Synopsys' Technology Access Program (TAP-in), EDA vendors and designers can immediately download the format and build interoperable tools and seamless flows based on SAIF. In addition, EDA standards organizations have direct access to SAIF for creating standards. The result is increased innovation and productivity for the design

Also announced at the EDA Interoperability Developers' Forum is the release of the new OpenVera parser. The OpenVera parser enables EDA developers to integrate tools with minimal effort, while saving time and risk normally associated with developing independent interfaces. The parser enables all EDA tools to follow the interface standard, ensuring continual compliance with OpenVera while greatly improving interoperability for EDA customers.

The SAIF format is available for immediate download at no cost at:
www.synopsys.com/tapin. Customers and EDA developers can access the OpenVera parser at www.open-vera.com when it becomes available in November 2002.

Mentor Graphics Corporation announced version 3.0 of the ICX signal integrity solution, a PCB signal integrity tool that supports SPICE, IBIS and VHDL-AMS in a single simulation environment. ICX 3.0 leverages Mentor's ADVance MS (ADMS) simulation technology to enable users to employ signal integrity models created in multiple languages simultaneously for full board-level verification with improved flexibility and accuracy and shortened design times.

The tool was created to address the signal integrity and timing challenges caused by higher clock frequencies and signal edge rates of high-speed, digital PCBs, ICX 3.0 makes simulation more efficient and accurate. This solution should shorten design times and improve system performance and also give IC vendors more behavioral modeling options for their devices. The company also announced the Tau 3.0 board-level timing solution, which now offers improved integration with ICX.

Monterey Design Systems rolled out Dolphin RTL ­ a second-generation RTL-to-GDSII solution, which is the result of an eighteen-month collaborative effort between Monterey and

Dolphin RTL blends RTL reader and logic structure generation technology from Synplicity with physical synthesis capabilities from Dolphin into a single solution. It uses Synplify ASIC technology to quickly generate an initial logic structure independent of wire loads and then performs tech mapping and logic optimization using Monterey Progressive Multi-objective Refinement (PMR) technology to meet timing and other design constraints.

Agilent Technologies Inc. introduced the latest version of the Agilent Advanced Design System (ADS) intended for design engineers creating RF, microwave and wireless communication products. ADS 2002C provides advances in simulation technology and usability for RF system, circuit and physical design.

ADS 2002C verifies design performance earlier in the development cycle by expanding solutions that integrate ADS with Agilent instrumentation. Advances in the software over the previous release include new capabilities that add significantly to Agilent's integrated ADS solution, including a multi-threaded Agilent Ptolemy simulation, a TD-SCDMA Design Library and a link to Agilent's ESG Signal Studio software, the company explained.

Agilent ADS 2002C comes with a new feature that adds circuit and physical co-optimization to co-simulation with layout components introduced earlier this year that allows ADS to adjust both circuit component values and layout dimensions to optimize physical and circuit performance. The co-optimization with layout components feature uses ADS' industry-leading EM simulator, Momentum, and features including RF mode for fast analysis of electrically small circuits and arbitrary polygonal mesh for high levels of accuracy and speed.

European independent microelectronics R&D center,
IMEC, has developed a local wavelet transform (LWT) IP block to reduce the memory requirements in wavelet-based image compression. Wavelets are increasingly used in image compression schemes because of their scalability features, which enable new functionalities such as progressive transmission, automatic adaptation to network and terminal resources. The LWT, based on block-based wavelet techniques, reduces the memory access cost by roughly a factor 3 while producing results equal to those of non block-based wavelet techniques, IMEC said.

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-- Ann Steffora, EDACafe.com Contributing Editor.


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