November 25, 2002
Outlook is Up-beat as COT Panel Offers Constructive Advice
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Panel Backs off of Moore's Law

On a day that Wall Street dramatically posted its largest point gain in many months, a panel of CEOs representing various nodes along the semiconductor design and manufacturing chain spoke optimistically about economic recovery and proved determinedly bullish about the future of the technology sector.

The panel included Jacques Benkoski, President and CEO of Monterey Design Systems, Levy Gerzberg, President and CEO of Zoran, John Bourgoin, Chairman and CEO of MIPS Technologies, Mark Templeton, President and CEO of Artisan Components, Jack Harding, Chairman, President and CEO of eSilicon, and Yoav Nissan-Cohen, Co-CEO of Tower Semiconductor.

Hosted in Santa Clara by EDA vendor Monterey Design and moderated by the ever-enthusiastic Erach Desai, electronics analyst at American Technology Research, the group attempted to answer the question posed by Monterey's Benkoski – Has the “No Economy” Killed IC Design?

Benkosi defined the No Economy as the train wreck that resulted from the collapse of the New Economy – the New Economy having destroyed the Old Economy. Like many, he attributed the collapse of the New Economy to overspending in the and telecommunications sector. He said the No Economy is characterized by technology moving too far ahead of the adoption curve, as well as escalating engineering costs combined with reduced volume-production opportunities. He illustrated his point with a graphic that indicated the cost of the various phases of product development across time. For devices designed to .18-micron processes and above, he argued that a satisfactory ratio exists between
the costs of functional design, physical design, and mask lay-out versus the subsequent revenues associated with volume production. Benkoski pointed out that in today's emerging technologies, however – at 90 nanometers and below – that ratio between development and volume production becomes unacceptable and devoid of adequate profit margins. These weakened profits are adding to the woes of the semiconductor industry, he said.

Benkoski suggested that a COT (customer-owned tooling) flow might offer a solution to the dilemma posed by the technically-challenging nanometer process technologies by stimulating a more efficient design flow, tighter integration between design and manufacturing, and lower NRE (non-recurring engineering) and production costs. In Benkoski's scenario, foundries would begin to adopt a broader role in the design chain akin to the fabless ASIC model. He challenged the EDA industry to rethink their existing business models and industry strategies, “to roll up our sleeves, and make it happen.”

Zoran's Gerzberg – manufacturer of consumer products – was not so easily swayed by Benkoski's hypothesis: “The economy today is the same as before. The [profit] equation has not changed, but the parameters and landscape have changed.” He pointed out that Benkoski must be a “software guy” if he thinks that once a product has gone to volume production, that profits follow automatically. He said the recent obsession with time-to-market has proved a fatal one – that time-to-profit should always have been the over-arching concern, especially in the consumer market. He said Comdex still drives the “biological clock” in his market and
there, “the ASIC model still works.”

Subsequent speakers, though wandering off-topic a bit, nonetheless provided insight into the current relationship between various players in the troubled semiconductor industry. Bourgoin, from Star-IP provider MIPS, said the IP model – broad licensing of design cores that shares development costs across a large customer base – should be extended to the concept of “shared R&D,” a concept the other panelist immediately rallied around. He said his market is being driven by customers who already have a design platform in place, while his secondary customer base is just trying to get to market quickly.

Artisan's Mark Templeton, as a spokesman for library vendors, said foundries today may be risking a great deal to try to compete with the likes of IBM and ST Microelectronics by attempting to provide complete services. As the foundries attempt to move aggressively to smaller geometries, he said, they're often unsure if their new design rules will actually work. Customers who are early adopters have to be wary and to determine for themselves what is really manufacturable and which processes they should back off of.

With little acknowledgement that things may have changed over the last several years, eSilicon's Jack Harding waxed poetic about the need for supply-chain management within the context of a disaggregated semiconductor industry. He said he offers services to customers who need to bridge the communication gap across the various players – thermal and packaging experts, DFT (design-for-test) teams, and a host of other experts who now reside in different corporate entities due to disaggregation. His comments seemed to suggest his market niche has suffered little impact from the tech sector downturn.

Foundry veteran, Tower's Nissan-Cohen, responding to a question from Desai, agreed that there has been a manufacturing discontinuity at 130 nanometers and below. He said that, until recently, “Our DNA [in the foundry business] has always said 'shrink, shrink, shrink.' Moving from one technology node to another was an obvious way to reduce costs.” He said things have definitely changed, however. Smaller geometries is the wrong obsession for today's market conditions. Pushing the physical limitations of Moore's law should be put aside, he argued, in favor of closely monitoring the economic limitations of a product. More efficient design should be the emphasis, rather than
“running to a new technology node.”

Desai asked if the industry is now at a point where a particular technology node is going to last a lot longer. The panel agreed, to a man, and seemed distinctly relieved at the prospect.

Industry News

Applied Wave Research Inc. announced a technology licensing agreement with Synopsys, Inc. that enables AWR to integrate Synopsys' HSPICE analog and mixed-signal circuit simulation solution into AWR's high-frequency design environment. This agreement will provide radio frequency integrated circuit (RFIC) designers with improved simulation performance and reduced development time in designing large-scale RFICs used in wireless and wireline appliances. AWR provides a front-to-back, high-frequency design solution for full-custom, analog, and RFIC design, while HSPICE provides analysis capabilities and supports a wide range of device models. AWR expects to deliver a solution based
upon the Synopsys HSPICE technology in the first half of 2003.

Atrenta Inc. and Agere Systems Inc. announced that Agere has selected Atrenta's SpyGlass predictive analyzer as their ASIC hand-off tool. SpyGlass analyzes gate-level netlists for design rule violations, allowing ASIC customers to identify potential design issues before handoff for final design and manufacturing. Agere will provide SpyGlass software to its customers through a web-based delivery method. SpyGlass supports industry standard file formats like Verilog, VHDL, and Synopsys Liberty. For custom rule development, SpyGlass interfaces with C and PERL development languages to allow Agere to develop their library-specific rule deck. The C interface provides development of complex
memory and compute-intensive audits. SpyGlass provides analysis of Verilog and VHDL code early in the design process.

Agere has extended the capability of Spyglass by providing Agere specific rules for analyzing gate-level netlists for design rule violations in such areas as overloaded drivers, undesired clock interactions, electromigration violations, and IP-specific errors. The Agere-specific rules allow SpyGlass to detect potentially fatal design problems. SpyGlass, with the Agere rules, performs both electrical and topology analysis, identifying areas of poor implementation.

Cadence Design Systems, Inc. announced that Advanced Semiconductor Engineering, Inc. established an analysis-driven IC packaging design flow based on the Cadence Advanced Package Engineer (APE) . The deployment of the new ASE design flow allows engineers on both sides of the design and manufacturing relationship to analyze the system interconnect and to optimize package performance in the entire system. APE provides package-level interconnect characterization and signal integrity analysis so engineers can perform design trade-offs between silicon, package, and board. This relationship supports the Cadence Design Chain Initiative. The Cadence SPECCTRAQuest for IC packaging
design and analysis tool has being integrated in the ASE design flow. SPECCTRAQuest employs a methodology that allows development of constraints for the interconnect through pre-layout exploration, constraint-driven interconnect implementation, and concurrent validation.

Comit Systems, Inc. announced sales of the Fiesta CVXT Verification Environment, part of an integrated toolset for automatic generation of code and documentation within a compatible verification environment, as well as design entry and verification. Fiesta CVXT Verification Environment exemplifies the trend in tools that link Verilog and tcl by offering the functionality option as an alternative to what have historically been expensive SoC verification tools. The Comit verification environment carries no maintenance fees.

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-- Peggy Aycinena, Contributing Editor.

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