December 16, 2002
Tick Talk at Tau
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Big things come in small packages
If you're struggling with the thorny timing issues that crop up in deep-submicron design, you've missed a chance to share your sorrows with other like-minded individuals. The 2002 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems - the Tau Workshop - took place in Monterey, CA, on December 2nd and 3rd. Sponsored by ACM/SIGDA in cooperation with IEEE, with additional support from Cadence, IBM, Intel, and Magma, this is a little conference that carries a big wallop.
The last Tau Workshop was held in late 2000 when, in a different economic clime, more than 100 attendees came together to discuss timing issues in design. IBM's Chuck Alpert, 2002 Technical Program Chair, said that due to the severely restricted travel budgets endemic to the industry today, attendance at this year's Tau Workshop was closer to 65. But he said the workshop was so successful - despite the reduced attendance - and the technical discussions so critical to deep-submicron (DSM) design, that workshop organizers may decide to reconvene sooner rather than later - in 12 to 14 months rather than the 24-month interval between workshops that has been the norm in the past.
“In retrospect, we should have had a meeting in 2001,” Alpert said, and added that the timing closure problems cropping up in DSM design are coming on too fast to wait two years between workshops. “We don't know what the interconnect delay's going to be in deep-submicron design, neither are we able to predict the timing problems in the presence of crosstalk.”
Though some who attended the workshop may disagree, Alpert argued that the stand-out technology on the table this year in Monterey was statistical timing - a strategy, he said, that appears destined to overtake static timing as the guiding principle in design. He offered the caveat, however, that predictions with regards to statistical timing may prove similar to those that persist in saying the end is near for CMOS scaling. Alpert paraphrased Tau keynoter Ivan Sutherland from Sun Microsystems Laboratories: “It's clear what the future is - it's just not clear when it's coming.”
improving the transistor's switching characteristics. AMD demonstrated a functioning FinFET with a gate length of 10 nanometers in September of this year.
AMD also presented two papers detailing success in building transistors with gates made from metal, rather than today's standard polysilicon. The nickel-based gate technology holds promise for significantly increasing transistor performance by improving electrical current flow through the transistor. When properly implemented, metal gates eliminate the current practice of placing impurities in the channel under the transistor's gate to achieve optimum switching characteristics. The removal of these impurities results in better electrical current flow, which in turn increases the transistor's performance capabilities.
Additionally, in conjunction with Stanford University, AMD presented a paper demonstrating a new Flash memory cell structure that may allow for scaling Flash memory beyond the 65-nanometer generation. The new structure uses polysilicon “nanowires” - some only 5 nanometers wide - to store an electrical charge. At these dimensions, memory cells demonstrate true quantum mechanical behavior and provide erase speeds several orders of magnitude faster than conventional Flash memory cells.
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) is talking about FinFETs these days as well. TSMC's new FinFET is known as the Omega FinFET, because the gate wraps around the silicon material that makes up the source and drain for each gate and creates a structure similar to the Greek character, Omega. The company demonstrated the first 25-nanometer transistor to operate within the power and performance specifications outlined by the International Technology Roadmap for Semiconductors (ITRS). The newly designed FinFET is the first 25-nanometer CMOS transistor to meet the ITRS target for high-performance operation at this technology node.
Standard CMOS is the dominant IC technology today, consuming less power in end applications than alternative technologies to date. The TSMC FinFIT indicates that CMOS technology could continue to scale to smaller geometries and higher performance for years to come. The ITRS roadmap is a technology guideline jointly developed by all the major semiconductor companies and their support industries. According to the roadmap, the industry should introduce 25-nanometer transistors in 2007. The next step will be to refine the manufacturing techniques for producing these devices in high volume.
pleased that we were able to amicably resolve the dispute with Mentor Graphics.”
testers, a system-level verification task otherwise performed after silicon samples have been produced.
Credence Systems Corp. announced that Diodes-China, a subsidiary of Diode Inc., has purchased its ASL 1000 test system for the company's advanced ISO-9000 manufacturing facility. Diodes-China, a manufacturer and supplier of discrete semiconductors, will utilize the test systems for production tests of mixed-signal devices for the automotive, communications, and consumer electronics markets. The ASL 1000 offers a configurable platform with the capability to tune the tester specifically for the device-under-test (DUT).
transistor-level simulation engine - using interconnect parasitics for the critical paths and clock networks, and dynamic values for voltages and currents rather than the ones and zeroes of traditional gate-level analysis.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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