May 05, 2003
Design to Silicon
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Several weeks ago, on April 8th to be exact, the Fabless Semiconductor Association (FSA) hosted an all day meeting in Santa Clara, CA - "The FSA Smart Fabless Models I & II Design Productivity and Outsourcing" seminar. Over a 100 people showed up and learned lots over the course of the day. Now "learned lots" is a relative phrase, as there's a fine distinction between absorbing facts and absorbing impressions. Presuming that "learned lots" means absorbing impressions, the FSA event was a very educational day.

The second panel of the morning included Gary Montgomery, Director of Product Marketing at MIPS, Tom Riordan, Vice President and General Manager for the Microprocessor Products Division at PMC-Sierra, and Aurangzeb Khan, Corporate Vice President and General Manager of the Cadence Design Foundry portion of Cadence Design Systems.

The three men addressed a variety of questions grouped under the rather large subject umbrella of "Design to Silicon" and as they each represented a distinct industry niche - MIPS in IP, PMC-Sierra in fabless semiconductor, and Cadence in EDA - Montgomery, Riordan, and Khan were able to compose a fast-paced overview of Design to Silicon, agreeing to agree on most of the larger issues.

To clarify the discussion, they started by defining System on a Chip. MIPS' Montgomery said, "It's an IC with a compute engine." PMC's Riordan said, "It's a chip with system-level integration including a microprocessor, custom logic, memory, and IP. It's a true system and requires that an operating system be included." Cadence's Khan agreed and referenced the Dataquest definition, "An SoC is a chip with system-level integration."

The definition was important to frame the follow-on question: "What percentage of current design starts and products coming off the line today are SoCs?"

MIPS' Montgomery said, "Of the ASICs our customers are producing today, 50% are SoCs. That number will increase to 75% within 3 years." PMC-Sierra's Riordan said, "[Approximately] 3 out of 30 projects have been SoCs over the last 2 years." Cadence's Khan said, "Of the 100 designs we see per year, two-thirds of them are SoCs." Clearly the numbers reflect the industry niche within which each man operates.

What about the availability of quality, commercial IP and the related commitment within corporations to design reuse methodologies needed to accomplish these complex designs? Not surprisingly, MIPS was all over that one. Montgomery said that quality IP is very available and definitely a reality today.

Riordan, however, said that PMC is not using microprocessor IP or analog IP. "We tend not to use IP from external sources. We're always working on bleeding-edge designs, and synthesizable cores often present high jitter issues." He added that in his own personal experience, internally developed IP is not really ideal either, never adequately documented by the development team, potential reuse within the company often compromised by lack of follow through. Cadence's Khan countered by saying that a company's commitment to design reuse was totally dependent on attitudes coming down from management.

That dovetailed with the next question on the state of affairs with regards to design collaboration across companies and continents - by all reports, the stuff of reality when it comes to SoC project development.

PMC's Riordan said he regularly deals with projects that span two continents and multiple time zones, and makes the whole thing work by using off-the-shelf design management tools. MIPS' Montgomery said, "Ten years ago, I was working on a project where the DSP portion of the design was done in Israel, the microprocessor was done in the States, and the project integration was done elsewhere in the States. It was an absolute nightmare! I've never forgotten that. It's much better today with the tools available."

Good news there, but what about system-level design and the languages needed to facilitate these huge designs? Cadence's Khan said the manual hand-off between software and hardware portions of big projects has necessitated the development and use of system-level languages, but transaction-level modeling, hardware acceleration for emulation, accelerations suites, and partitioning designs into manageable blocks is also crucial to the strategy. Khan added, verification continues to be the biggest stickler.

Meanwhile, popular wisdom tells us all that verification only gets "sticklier" as the process technologies gets smaller and sexier. MIPS' Montgomery said that shrinking geometries are linked to product volume - or should be, via a consideration of the economics involved. A company should defend the move to smaller process technologies and higher integration by demonstrating that increased production volume will support the move. He asked rhetorically, "When does a transistor becomes cheap? A higher degree of integration must be justified by a subsequent lower cost per transistor over a two year period."

PMC's Riordan was unforgiving in his thumbnail sketch of recent process technology migrations: "Every other technology migration [over the last few years] has been a disaster. We got to 0.25 microns late. Things went wrong. The tools weren't ready from the vendors. Then we went to 0.18 microns and it proved to be an absolutely magnificent technology. Even today, you could start whole new companies based on 0.18-micron technology. Then we moved to 0.13 microns. Again, it was an absolute disaster! Major vendors went to Cu and low-k [dielectric materials] at the same time. We needed to handle [additional] data because there were lots of extra vias. [Now we're looking] at 90 nanometers and 0.13
microns at the same time. 0.13 has been so late [coming on line], 90 nanometers [is a big question mark]."

Cadence's Khan was succinct: "You've definitely got metrology issues, plus design issues at 90 nanometers."

PMC's Riordan continued: "We need to manage these issues to get the larger design done. We [definitely] stubbed our toes in moving from 0.18 to 0.13-micron technologies. And 90 nanometers is creating a lot of anxiety, the biggest problem being leakage - along with speed, power, and reliability. And, we [also] need to find the best [design] practices to [address] areas of weakness in chip packaging and board design, where we're transmitting signals in the GHz range across the board. And, then there's the flip chip issues."

With so many problems, how is the industry managing the human resources needed to conquer it all? MIPS' Montgomery said, "We're trying to integrate analog into a digital arena. There's [clearly] a shortage of mixed-signal expertise, but there are still large numbers of [capable technologists] available." Not surprisingly, he added, "In the current situation, IP become [even more] important. We're starting to see more and more analog IP and we're seeing some help from the tool vendors there as well."

PMC's Riordan said, "We're making a large effort to keep our mixed-signal team together. And there are lots of [refugees] from the telecomm industry. We're starting to try to work with IP suppliers to avoid building things [from scratch]. But with only 500 pins on a chip [to access internal signals], there are large issues in mixed-signal design."

MIPS' Montgomery had a message for the EDA community: "Solve our verification problems. If we can have major blocks of a design commercially verified, [it will go a long way] to solving system-level problems."

Wrapping up, the panel laid out the Pain and the Potential.

MIPS' Montgomery said, "The cost of design is escalating. At 0.13 microns, mask costs are skyrocketing. We've got tens of millions of transistors [on-chip]. We've got big problems in Time to Market and Time in Market. Perhaps [we're beginning to see] products will last longer in the market if they come with re-programmability - where you can add new product shelf life through software. We've got to ask ourselves, 'What do you do to reach volume production successfully?' You extend an ASIC to an ASSP, and you have access to qualified and tested IP."

PMC's Riordan said, "Given that [level of] programmability, you'll have fewer designs, but you'll need more people [to develop the designs]. You'll have projects with more people and more [diverse] outcomes."

Cadence's Khan said, "We all want to go to 130 nanometers and beyond. How do we do these projects?" He answered his own question with a nod to his audience: "The fabless industry has always been good at partnering. We all need to specialize in building partnerships to move the entire industry forward."

Yep, lots to learn on a rainy day in Silicon Valley.

Industry News - Tools & IP

Altera Corp. introduced version 2.1 of its DSP Builder digital development tool that integrates The MathWorks' MATLAB and Simulink DSP development software with the Quartus II FPGA design environment. Version 2.1 allows FPGA co-processor development "in concert with" Altera's SOPC Builder system development tool.

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-- Peggy Aycinena, Contributing Editor.


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