June 02, 2003
Movers and Shakers
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Here's everything you ever wanted to know about two guys who are definitely household names in EDA - ESNUG's John Cooley and Magma's Rajeev Madhavan. I was delighted to have a chance to talk with each of them at length over the last several weeks and came away impressed, as I often am, with the energy and articulate vision the leaders in this industry bring to their work and our world.
Admittedly, not everyone sees eye-to-eye with these two particular men, their style or their opinions. Be that as it may, Cooley and Madhavan are among that small handful of people who are setting future directions in EDA.
back an hour later. Yep, definitely a busy morning.
Once we got into our conversation in earnest, however, Madhavan was relaxed, engaging, and seemingly happy to explain how he got to where he is today - Chairman, CEO, and Co-founder of Magma Design Automation in Cupertino, CA. If he was at all sleep-deprived, it certainly wasn't apparent.
John Cooley - Lots of folks in EDA like to throw around first names: Ray, Aart, Wally, Gary, Bernie, Penny, Jacques, Rajeev - and of course, Joe. But there's one icon in this industry who's definitely a last-name kind of guy, and that's Cooley. It's been a long time in coming, but I've finally had the chance to profile John Cooley and I have to say that, one-on-one, he's not half as scary as people would have you think. And though his raw candor during our conversation was not unexpected, his self-effacing charm caught me completely off guard. So please drop all of your pre-conceived notions and read on, as Cooley discusses Cooley.
Industry News - Tools & IP
covered, either with simulation or with formal verification. Structural coverage provides, for the first time, an automated metric that directly links coverage with functional error conditions in SoC and ASIC designs.”
“The three components of structural coverage are static structural coverage to identify verification points in RTL, simulation structural coverage to show coverage exercised by simulation, and formal structural coverage to measure verification by formal analysis. Static structural coverage reports how well each section of the RTL code is covered by assertions. Simulation structural coverage reports how well user testbenches exercise functional corner cases. Formal structural coverage measures the amount of formal analysis performed from each functional corner case, measured as a proof radius from the corner case.”
Agere Systems announced what the company calls “a significant technological achievement by integrating more ARM processors in a single microchip than any other semiconductor provider.” Agere says it integrated eight ARM cores onto a single ASIC and was able to provide customers four times the processing power on a single device. The company says the product was produced for a “leading wireless base station provider.”
Agilent Technologies Inc. announced the expansion of a technology alliance with Cadence Design Systems Inc. that the companies say will provide additional tools for wireless product development. This is phase two of the alliance and adds wireless system-level verification and layout analysis to previously integrated RF/mixed-signal IC circuit-level design offerings. The jointly developed products are expected to become available as early as the second half of 2003.
Also from Agilent - The company announced automated technology to provide fast passive component models to accelerate design of RF and microwave circuits used in cellular phones, wireless and broadband networks, radar and satellite communications systems. The company says its Advanced Model Composer is available with the Agilent ADS 2003A EDA software suite.
Alternative System Concepts (ASC) announced that it has initiated a Preview Edition program for its upcoming power aware behavioral synthesis product, code-named PACIFIC. The company says PACIFIC is used at the beginning of the design process to optimize designs simultaneously for power, timing and area - and “exploits” the Advanced Library Format (ALF), the impending IEEE standard 1603. PACIFIC automatically explores the design space and obtains optimal RTL architectures.
Ansoft Corp. announced a new version of HFSS, the company's 3D EM design and analysis software. The company says thousands of engineers use the product to design RF and microwave components, antennas and arrays, high-speed ICs, PCBs, and IC packages, and that HFSS Version 9 will increase design-flow efficiencies. Bernard Schmanski, of BAE Systems and HFSS v9 beta tester, said, “Ansoft has done an incredible job with all of the enhancements in HFSS v9. The increased functionality helps to simplify model generation and analysis, leading to a very positive overall experience."
Artisan Components, Inc. and UMC announced that long-term IP collaboration between the two companies is now focused on the development of a PCI-Express PHY IP core for 0.13-micron chip designs. The new core will be based on the PCI Express Architecture that has been proposed by the PCI-SIG (PCI Special Interest Group), which owns and manages PCI specifications as open industry standards. The modular 8-lane PCI Express 2.5Gbps PHY is designed to be a general-purpose I/O interconnect.
Barcelona Design Inc. announced the Dali class - which the company calls “the world's first data converter synthesizers” - running on Barceonla's Prado analog synthesis platform and based on the company's geometric programming synthesis technology. The Dali synthesizers provide synthesis of complex A/D and D/A converters in digital CMOS technologies. The first engine in the Dali class, which is a pipeline A/D converter engine with a range of 6-10bits and 5-80MSPS, will be released in September 2003.
next [product development phase] is going to attack sub-systems - an analog front end with a combination of several data converters, PLLs, etc.”
Cadence Design Systems, Inc. announced the release of the Cadence Aptivia Parallel Characterization option, which the company says will enable customers to reduce circuit validation time by 10x or more. The new option “parallelizes” Cadence Spectre SPICE simulations to characterize corners and variations, and enhances Aptivia, which is now integrated with Cadence Virtuoso Schematic Composer and Analog Design Environment. Cadence says the new option will help to ensure higher yields, while still meeting performance targets. Each option allows designers to parallelize up to four Spectre SPICE simulations. Designers can use any number of options simultaneously.
Also from Cadence - The company announced that Infineon has selected First Encounter for the silicon virtual prototyping of complex 130-nanometer and 90-nanometer ICs. Infineon says it will use the Cadence tool to generate and refine virtual prototypes of IC physical designs, including interconnect. The prototypes will then be used for feedback on SoC performance, physically feasible layouts, preliminary placement, and optimized floorplans.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.
Be the first to review this article