October 13, 2003
SystemVerilog in the news (again)
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Before you pore through all of this, let me warn you. This is a story without an ending. This week's Press Releases not withstanding (see below), the story of the research and corporate investments in system-level languages, and their subsequent implications in the EDA world, has just barely begun.
On the tarmac in Texas
Dennis Brophy, the ever politic and positive Chairman of the Accellera language standards body was sitting in an airplane on the tarmac Thursday in Austin, TX, waiting to take off when he was kind enough to put a call through to me via his cell phone. You've just gotta love technology.
Dennis was en route home from the first of four SystemVerilog Now! Seminars that are happening this month and next in various venues across North America. He told me that over 70 people had attended the Austin session and that upwards of a thousand people are currently registered to attend the conference across its four locations. I wanted to speak to Dennis about this week's SystemVerilog announcements out of Synopsys and Cadence. The announcements are as follows, abridged as always:
The news from Synopsys
“Synopsys, Inc. has announced its SystemVerilog Catalyst Program. The Program is open to EDA vendors, silicon and verification IP companies, and training services providers to benefit mutual customers by advancing tool interoperability and the availability of IP using the Accellera SystemVerilog standard. The company says that 30+ companies are announcing their support for SystemVerilog at the program's launch. Corporate members of the Program can gain early access to Synopsys' SystemVerilog-based tools for development and support of their respective SystemVerilog tools, IP and training products.”
“Current members include 0-In Design Automation, Alatek, Aldec, Aptix, Atrenta, Avery Design Systems, Axis Systems, Beach Solutions, BlueSpec, ChipVision, ControlNet, Doulos, Emulation and Verification Engineering (EVE), GDA Technologies, Interra Systems, InTime, Jasper Design Automation, Novas Software, nSys, Provis, Real Intent, Sequence Design, SiConcepts, Silicon Interfaces, Spike Technologies, Summit Design, Sunburst Design, Sutherland HDL, SynaptiCAD, Tenison, Tera Systems, Tharas Systems, TNI-Valiosys, TransEDA, VeriEZ, Verific, Verifica, Veritable, Veritools, Willamette HDL, and WSFDB Consulting.”
“Aart de Geus, Chairman and CEO at Synopsys, is quoted in the Press Release: 'SystemVerilog's enhanced design and verification capabilities are well positioned to deliver significant productivity and design quality benefits to the electronic design industry. Synopsys has a strong history of supporting open standards and is launching the SystemVerilog Catalyst Program to help ensure that our customers enjoy the benefits of SystemVerilog, including increased tool and IP interoperability. We look forward to working with current and future members of the SystemVerilog Catalyst Program on this joint effort.”
The news from Cadence
“As part of its strategy to ensure unified standards for advanced design and verification, Cadence Design Systems, Inc. announced support for SystemVerilog. Cadence is committed to accelerating the process of bringing SystemVerilog from a specification to a fully implemented international standard. The initial developer of the Verilog language and a pioneer in the concept of open language standards, as exemplified by the creation of OVI in the early 1990s, Cadence provides current and continuing support for the VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS, and VHDL-AMS standards.”
“During the next weeks, Cadence will roll out plans for SystemVerilog support in its Incisive verification and Encounter digital IC design platforms, as well as plans for smoothing the path of SystemVerilog through the Accellera and IEEE standards process. To drive this process, Cadence has named Victor Berman, an industry veteran in language standardization, to lead Cadence's language and standardization strategy.”
“Berman is quoted in the Press Release: 'Cadence supplies a very broad set of design tools and capabilities; my job is to ensure that the semantics of standards implemented at different levels and by different tools can be used together in a productive way. This is best achieved when standards are developed in a unified way with open input from all interested parties. I am looking to the IEEE to provide that unification in the evolution of Verilog.'”
“Berman has more than 20 years of experience championing standards issues in the EDA industry, which included the standardization of VHDL and serving as chairman on the IEEE Design Automation Standards Committee for 6 years. To date, Cadence has donated and opened up more than a dozen major proprietary languages and formats to the industry, including Verilog, GDSII and SDF. The Incisive verification platform-the only platform in the industry that supports all broad languages on a single kernel-is working proof of Cadence's commitment to standards.”
Comments from Accellera
First I asked Dennis why he thought Cadence wasn't named as part of the Synopsys program, and why Cadence might suddenly feel the need to issue a Press Release announcing support for SystemVerilog at this particular moment in time.
Dennis graciously declined to comment: “It's not really appropriate for me, or for Accellera, to comment on the Cadence announcement. I would prefer you talk to Cadence about that. I don't know what their specific motivations are, but I do know that this stuff is becoming more real [every day]. End users are helping everybody to see what they would like to exploit in the language. We certainly welcome Victor Berman back to the industry. His history in the development of standards is long-standing and well known, and he's trusted by all of us. He'll now be one of the Board Members for Accellera. We've always enjoyed working with him and we look forward to having him on the Board.”
I asked Dennis why it's important for companies like Cadence and Synopsys to drive and/or endorse the move to SystemVerilog. Is it to protect their ASIC designer customer base or does it reflect a legitimate evolution in the technology?
Dennis said, “I definitely think it's part of a legitimate evolution. Designers want their design data and their verification data to be interoperable. People have asked all of us to adopt the whole standard, so that there's a guarantee that any verification data has portability and reuse. It's a pretty pro-designers statement that's being made right now [by way of these company endorsements]. It also represents a broadening of support [for the language].”
As I have many times in the past, I asked Dennis to clarify his understanding of the situation twixt SystemVerilog and SystemC. Is there really a battle here or are the two initiatives complementary?
Dennis said, “I think the way most of us look at it is that it's complementary, not mutually exclusive. SystemVerilog, in moving from 3.0 to 3.1, now includes direct programming language interfaces, which frankly are C++. If anybody does work with SystemC, it should be easy to reuse that SystemC [design] in the context of a SystemVerilog design. If you're going to do architectural exploration in SystemC, SystemVerilog is a natural companion to SystemC.”
I asked Dennis to be patient with an additional oft-repeated question: Will hardware and software guys ever communicate?
Dennis chuckled: “Well, they all must be doing some of that already because they've sure got lots of electrical devices [out on the market today] with loads of RTOS and software content. I think that system [design techniques] are becoming effective. Could the communication be better? Sure! Can we help to encourage the communication? Yes, we can and I believe we are.”
[experienced up until now] by attending DAC.”
If Dennis is right, maybe you should plan on attending.
(Editor's Note: Don't forget that Dennis Brophy also has a day job. He's Director of Strategic Business Development for Mentor Graphics)
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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