December 15, 2003
True Circuits' Stephen Maneatis
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Stephen Maneatis is the CEO of True Circuits, Inc. The following commentary on the business and technology of analog IP were made during a recent lengthy phone call and provide an interesting point/counterpoint to the comments from Adam Kablanian in the
December 1st issue. Please read for the larger lessons, not for the specifics or the messaging about the company.

“True Circuits is a provider of analog and mixed-signal IP for the semiconductor, systems and electronics industries. Our focus now is on timing IP, which we license through library partners and directly to end customers. We're seeing a strong pickup in a number of market segments right now - both with IDMs and with smaller AISC and FPGA firms - which is exciting for us as it means an increase in licensing of our IP.”

“These days, analog and mixed-signal IP are viewed as one and the same. A customer is either buying digital or analog/mixed-signal IP. These involve two different areas of design expertise with different competencies. Of course, it's analog/mixed-signal IP that's gaining in importance as more and more chips are developed for communication applications, so that is good for us.”

“There are a lot of physical issues at 130 nanometers or 90 nanometers that an analog engineer has challenges with - shrinking a digital design is doable as you move to smaller process nodes, but shrinking an analog circuit is just not that simple. And right now, we're seeing a shortage of experienced analog engineers. For instance, we hired an employee within this past year who was a digital engineer - a very smart guy - and with some training and mentorship, he was able to pick up on the analog issues and successfully perform mixed-signal design work. But more typically, you've got engineers who are trained, or are passionate, either in digital or in analog - but not both.”

“I see two issues at work in the IP industry today. First analog/mixed-signal design is getting harder and harder, while at the same time, large companies have been dispersing these niche design teams as part of their downsizing efforts and small ASIC and FPGA companies are now entering the market. Over the last several years, this has made outsourcing IP development the only way many of these companies can complete their complex chips. If you look back 5 to 10 years, you would see that large companies had large engineering staffs to work on timing and interference designs and related issues. But as we've seen the strong trend toward outsourcing over the last couple of years, many
companies no
longer have that kind of expertise in-house. Design reuse and third-party IP have now become a necessary and economical way of getting products to market without having [to bear the burden of] in-house analog/mixed-signal design teams.”

“Second, there are concerns about the quality and reusability of IP. Is it practical for a company to license and use IP from a third party that is basically a black box and be confident that the IP will work after it's integrated into their design? Related to that, can a customer truly reuse the third party IP and thus amortize its cost over the lifetime of the product? This second issue is where companies, both big and small, have an aversion to licensing IP.”

“But the biggest concern for customers is whether the IP they've licensed will work, and on first silicon. If I can tell them that this or that piece of IP has been proven in silicon, they're more confident about using it. When you're a vendor that offers a large portfolio of IP across any vendor or process, not every design in the portfolio will have been proven in silicon. Customers will naturally have concerns about that, particularly as they know that integrating IP into small geometries and dealing with ever changing standards is tough. So our focus is on providing timing IP that is very robust and has been optimized for performance throughout wide operating ranges. We want the
customer to
be able to drop our IP into their chip and know that it's broad enough in its design and flexible enough by its pin-programmability that changes in the larger design of the chip can be accommodated by the original piece of IP rather than requiring compromises.”

“Of course, we always emphasize to our customers that we're really good at what we do - that our IP is robust, standardized, reusable, and that we provide the support and training required to use it optimally in their chip application. If our first engagement with a customer goes well, they're more at ease with considering a second engagement with us. We feel what really distinguishes between IP companies is whether the IP is standardized enough to use and reuse - and that's why we've made a great deal of effort to develop the core circuit technologies and the design flows that allow us to produce each piece of IP in a standardized way. Our IP is available across a range of
process generations, and fabrication vendors. We do considerable amount of R&D and are constantly improving our circuit technologies. Using our proprietary CAD environment and design flows, we can easily port new technologies to new or old process generations and to any fabrication vendor. We've got a broad portfolio of timing IP - DLLs and PLLs - and our customers can pick any item from our IP catalog, license it, and know that we'll provide a hard macro ready to integrate into whatever chip or circuit they're designing. It's a seamless process.”

“Again - this is something that distinguishes the different IP companies. Some third-party vendors just want to throw their IP over the fence to their customers and let the customers struggle with the integration. That's not our business model. We spend a great deal of time optimizing our designs and user documentation before sending an IP hard macro to a customer, and although we are always ready to provide support, our IP is such that in more than 50 percent of the cases, a few phone calls at the outset of the integration process is all that's needed for the customer to proceed. The second time around rarely even requires a phone call. Our goal as a company is to get to the point
that we
need to offer zero support - that we've understood a customer's requirements and provided the right IP that they can easily integrate and reuse. If a customer is satisfied the first time and they know we've got good IP and a good support model - we'll win that customer for life.”

“Meanwhile, there's an evolution underway in the industry with regards to licensing models - models that build up-front relationships between the IP provider and their customers. Right now, we have a license fee model that does not involve royalties. Our customers pay a license fee at various milestones - at delivery of the IP, at tape-out to fab, and when the IP is proven in silicon. If the customer wants to use that piece of IP multiple times in their chip design, they can do so for no additional fee. However, if they want to use it later in a different chip design, they only pay a reuse license fee - typically 50 percent of the original first-time license fee. There is no per-part
so all IP cost is known and paid upfront.”

“There are potential issues with IP piracy. We track reuse by building relationships with the companies we work with. Of course there's an honor system associated with all of this. And now that we're working with more and more customers, we are happy that the VSIA tagging system - complete with IP reference number - is in place so the major fabs can look at the appropriate layer in a chip and verify that a particular piece of IP is being used by that customer.”

“Our current strategy is primarily based on the honor system. It requires the players [in the design and manufacturing chain] to report out on their use of our IP. Our biggest concerns are, therefore, that our IP can be reused by a current customer without a fee being paid, or worse, that it might be reverse engineered or propagated - ending up systematically incorporated into other companies' technology. At this time, we have quite a number of patents either issued or pending on our IP. We always make sure the patent process is in place before we publish in leading technical journals - and we make sure that the licensing agreements are clear and up to date.”

“Customers have intellectual property protection issues of their own. When we first engage with a potential customer, we always sign mutual NDA agreements to ensure confidentiality with respect to their pending chip project and our IP. There are actually a number of legal remedies that you can pursue to protect a situation. After all, potential customers have to be able to look at our IP and understand if they can integrate it into their code, so there's an inevitable degree of visibility there, although we never provide customers with the actual schematics. We're always aware, however, that when
someone has got your GDSII and the things that go with it - they might, unfortunately, decide to
pursue a direction that's parallel with what we've done.”

1 | 2 | 3 | 4 | 5 | 6 | 7  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, Contributing Editor.


Review Article Be the first to review this article
CST Webinar Series


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy