January 19, 2004
ATE and/or Embedded Test
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

If you're an aficionado of Test, autumn is your special season. The International Test Conference - ITC - is a distinctly fall event, attended each year by legions of loyal members of the Test Fraternity. This year ITC will be held in Charlotte, NC, from October 26th to the 28th and, as always, I'm sure a good time will be had by all.


Consider the following conversation then, to be a January hors d'ourve in advance of the year's main course being served up way off in October. It's a roundtable discussion between four guys in Test, guys who know a lot about the subject and who were willing to answer a set of questions about the current integration, or lack thereof, between ATE [automated test equipment] technologies and DFT [design-for-test] technologies. The conversation took place in a conference call on Monday, January 12th, and the participants included:


1 - Stephen Pateras, Senior Director, Corporate Product Marketing, at LogicVision Inc. - received his Ph.D. in EE from McGill University.


2 - Ric Dokken, Co-Founder and Vice President of Software Development at Inovys Corp. - has a BSEET from DeVry College.


3 - David Hsu, Director of Marketing for Test and Formal Verification at Synopsys, Inc. - has an MBA from Santa Clara University, an MSCS from Stanford, and a BSCS from MIT.


4 - Sergio Perez, Vice President for Sales at Advantest America Inc. and Founder/Current Vice Chairman of the Semiconductor Test Consortium - has a BSE from Harvey Mudd College and an MBA from Harvard.


Meanwhile, before you start in on the roundtable, it might be useful to hear how the companies that each of these gentlemen work for position themselves.


Per the company: “LogicVision provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip.”


Per the company: “Inovys Corp. supplies advanced test solutions for semiconductor companies who require economical structural ATE systems and EDA-to-Test software. Inovys has pioneered the low-cost desktop tester which combines seamless ATPG [Automatic Test Pattern Generation]-ATE-EDA integration with advanced failure analysis tools utilizing DFT methodology.”


Per the company: “Synopsys, Inc. creates leading EDA tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.”


Per the company: “Advantest is a world leader in the test and measurement industry, supplying cutting-edge products and services vital to the growth of the electronics, telecommunications, and semiconductor industries. Advantest's businesses can be classified into one of four categories: optical measuring instruments, semiconductor test systems, handler & device interfaces, and nanotechnology.”




The ATE/Embedded Test Roundtable


Q: Where are you all sitting at this moment and how did you get interested in test?


Stephen: I'm sitting in San Jose. I got my Ph.D. in the area of test.


Ric: I'm sitting in Pleasanton, California. Way back in 1986, I started at LTX as a college grad.


David: I'm sitting in Sunnyvale, California. I started in test by supporting VLSI technology and the “vector hospital” back in 1986.


Sergio: I'm sitting in Chandler, near Phoenix, Arizona. It's been so long for me [laughing], I don't remember how I got involved in test.


Q: Geographically, where are your customers located?


Stephen: LogicVision's customers are all over the U.S., and in Japan, Taiwan, and Europe.


Ric: The Inovys customer base is global.


David: That's an interesting question. We measure market penetration by our Design Compiler installed base. At this point, Synopsys is probably at one test license for every two synthesis licenses out there.


Sergio: The Advantest customer base is global in nature.


Q: Can we reduce the costs associated with “Big Iron” ATE, or do we really even want to? What about “Little Iron” - workstations or PCs being used as less expensive post-production test equipment? Also, who coined the phrase, “embedded test.”


Stephen: You've already seen that [cost reduction]. Everyone from the Big Iron companies to all of these DFT companies are certainly coming out with lower-cost ATE. But, the largest portion of the costs of test is not in the equipment. They're in the handlers, the probe cards, the engineering. While you can reduce the cost of ATE, it's the human resource costs that [constitute the majority of the expense in test].


Ric: What you're seeing today is that some IDMs [integrated device manufacturers] have integrated their own low-cost test vehicles and are using that equipment for the sole purpose of reducing test costs.


David: It's not easy for me to say. Originally, 3 years ago or more, when we started working with the ATE vendors, they thought we wanted to take away some of their revenue. But they can now see, that that has not been the reality. In terms of whether customers are using Big Iron or Little Iron, those decisions are being made based on objectives other than just cost.


Sergio: It's a lot more complex than just reducing the cost of ATE. We reduce costs with each generation [of ATE equipment that we produce], in synch with Moore's Law. However, ATE capital expenditure [for a company] only represents 25 percent of the total cost of test. Everything that we do at Advantest, we do to reduce that cost. But ATE is just one of many tools that are used in test.


Stephen: We see embedded test - and by the way, LogicVision coined the phrase, “embedded test” - and DFT, in general, as not just a way of reducing the cost of test, but as a way of keeping up with the test requirements. You can't test 50 million transistors on a chip, or 50 million gates, with just an ATE approach. You need to have something on-chip, as well. We're now seeing that belief accepted by a larger portion of the industry [than was previously true] - particularly in the area of memory BIST [built-in self test].


Sergio: There's agreement that at 250 million transistors [on-chip], you can't test without having embedded structures on the chip. I agree 100 percent that we need the help of embedded test [for these complex devices].


David: I'll agree with that, but the question remains - is there a commercial market for embedded test. Up 'til now, customers have needed this [capability], but as vendors, we need to enable this [process], so that buying licenses for [tools that insert test structures on-chip] is feasible. The business issues here aid the technology issues.


Ric: I would echo what's been said here - the point that the transistor count today is such that [the chip] can't be tested just by using a functional testing methodology. At the same time, the [design] mechanisms that employ embedded test are, by nature, lowering the cost of the tester equipment.


Q: How wide spread do you think the acceptance is for embedded test? Is the reduced cost of on-chip real estate having an effect?


Stephen: Everyone has a different pain level, working at different design complexities, so the adoption rate for embedded test varies for every company. The fact that the testing of embedded memories is always done using embedded test [means that for memory vendors, embedded test is a reality]. Embedded test for embedded logic or some hybrid [of scan and BIST] using tools from Synopsys or Mentor, means that maybe we've got 50-precent acceptance for logic designers. [Meanwhile, going forward], you're going to see more embedded test for mixed-signal structures.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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