May 17, 2004
High Speed PCB Design
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Many years ago I was involved with the development of PCB design software. From today's perspective older PCBs were simple the means to hold ICs in place. PCB layout was largely an exercise in economics and topology. A lot has change over the years particularly in the area of high speed PCBs.
In a phone conversation John Isaac, Mentor Graphics' Director of Systems Market Development, identified three drivers of high speed printed circuit board design. First, significant advances in integrated circuit technology translate into higher clock speeds, edge rates and pin counts on the board. Today, asynchronous I/Os serial data channels operate in the multi Gigabits-per second range. Second, there is increasing use of high density, high performance and high pin count Field Programmable Gate Arrays. Third, there have been considerable advances in PCB fabrication including embedded passives, high density interconnect (HDI), microvias and advanced packaging. All these factors impact
the way printed circuit boards must be designed. In particular, they translate into the need for better analysis tools for timing, signal integrity, EMI/EMC and power delivery. Old rules of thumb will not suffice nor will only post-layout analysis. In addition on the business side there are trends in the end user community towards enterprise globalization, emerging markets and outsourcing that impact who, where and how designs are being done.
Let us examine these factors in more detail, starting with the increasing need for collaboration.
such as acquisitions.
Companies have a long tradition of outsourcing the manufacture of printed circuit boards to Electronic Manufacturing Services (EMS) vendors. The leading EMS vendors such as Flextronics, Solectron, Sanmina-SCI and Celestica have operations around the globe. These vendors offer design services and design collaborations. They have the expertise regarding their own manufacturing processes, part cost and availability and so forth. Collaboration between EMS vendors and designers during the early stages of design can significantly impact the cost and time to market by avoiding problems rather than having to solve problems late in the design cycle by costly re-designs and re-manufacturing
processes. Lastly, there is increasing use of outsourcing of the design activity to emerging markets. The Chinese in particular are growing in their sophistication regarding PCB design to serve both their own domestic market and their American and European outsourcing clients. The AP region is the fastest growing for PCB design tools.
Collaboration requires sophisticated secure web-based data management and parts library management capabilities with appropriate role and project based access rights. These capabilities include check_in/check-out, revision control, system administration tools, Bill of Material extraction and so forth. Such a system should support the development of design variants as well as design re-use.
PCB Fabrication Advances
There are many devices types found on PCBs including ball grid arrays (BGA), Chip Scale Packaging (CSP), Flip Chip (FC) or Direct Connect, Wafer level packaging (WLP), Microvias and embedded components whose properties must be considered during simulation and layout.
A microvia is defined as a blind via with a diameter 0.005 or less that is usually drilled from the top and/or bottom layer(s) to the first or second adjacent internal layer. Normally the adjacent internal layers can be used to redistribute the signals to other areas of the board where conventional through-hole vias can be used or they can be used as power/ground planes or a combination of both.
Microvias offer advantages over plated through-holes in terms of overall board size reduction, layer count reduction and increased route or interconnect density. Microvias permit reduced component-to-component spacing, which increases the number of routing channels available on each layer. Microvias also permit the connecting of components in close proximity without the need for additional real estate to complete fanouts.
Mentor Graphics notes that the Sony HandyCam has 1,329 passive components and 43 active components, a ratio of 31:1. They cite cell phone examples from three vendors that have a passive to active ratio around 20:1. Discrete passive components (mostly resistors and capacitors but also inductors, transformers and RF elements) take up considerable board space driving up cost and board size. There is also an issue of parts management during design and manufacture. As an alternative, embedded component technology (ECT) reduces board size, weight and assembly time, while improving performance and reliability by reduction of solder joints. ECT is the art of embedding passive or active
components within a substrate. For high-speed systems, embedded passives - specifically embedded resistors - can shorten signal paths, reduce series inductance, and reduce electromagnetic interference (EMI) and crosstalk. This embedding can take place on a single layer of material, a combination of material layers or even can be achieved by placing a component within a cavity in a substrate. When resistors are embedded within a substrate, they can end up 10 to 20 percent off the target resistance due to the screening process and material inconsistencies, which is known as process tolerance. Laser-trimming techniques are used to bring the resistor into range.
The Advanced Embedded Passives Technology (“AEPT”) Consortium is a group of companies working together to develop the embedded passives, resistors and capacitors, technology.
The impact of these fabrication and packaging advances on printed circuit board design is that the tools used for simulation, placement, routing must be cognizant of their properties (electrical, physical, electromagnetic, ..), behavior and their interactions with other components. This means, for example, that embedded component and their properties (including value range, tolerance, power rating, voltage rating, trim allowance, minimum size, etc.) need to be synthesized automatically from a schematic into an actual substrate design.
Consequences of Advances in IC technology
As clock frequencies increase, timing margins decrease. The higher speeds and faster rising times mean that analog issues such as cross talk, phase and amplitude distortion, ground bounce, and so forth which might have been ignored in the past must now be considered. Simulation tools must examine issues of timing, signal integrity, and EMI/EMC.
As ICs switch faster and faster printed circuit boards suffer from signal degradations such as overshoot and undershoot, ringing, cross talk and excessive settling delays. Ringing refers to signal distortion caused by multiple reflections. The reflections are generated due to impedance mismatches. Where these reflections overlap, the amplitude of the ringing may increase with the potential to cause false triggering of devices. At high speeds, even board vias have significant inductance and capacitance and can cause reflections. Crosstalk is caused by both inductive and capacitive coupling between parallel lines. Inductive coupling is the result of the magnetic field that surrounds each
conductor while capacitive coupling exists between conductors that are at different potentials. There are two types of crosstalk, forward and backward as defined relative to the direction of current flow in the driven or aggressor line. These types behave quite differently. Although the magnitude of forward crosstalk increases as the length of the coupled region increases, its pulse width remains nearly constant and independent of the length of the coupled region. Backward crosstalk, on the other hand, has a nearly constant magnitude that is independent of the length of the coupled region (as long as the coupled region is "long enough"). But its pulse width is twice as long as the coupled
region. The maximum amplitude, and even its polarity, can be a function of impedance loading at the front (near end) of the victim trace.
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-- Jack Horgan, EDACafe.com Contributing Editor.
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