May 24, 2004
Low Power Soc Design
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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In highly mobile, frequently wireless applications like cell phones, personal digital assistants, palmtops and multimedia players the trend is towards smaller and lighter weight packaging yet with increasing functionality and lower price. The demand from end users for increased battery service life is considerable. Expectations for several hours of active use and much longer for standby operation are the norm. For high performance, non-battery operated systems such as workstations, servers and networking computers there are concerns regarding packaging expense, cost for cooling and fans for heat removal, and reliability due to temperature effects. According to one industry
the chip failure rates double for every 10 to 20º C increase in operating temperature under normal ambient conditions. Laptop and notebook computers have power related issues common to both.

Power density measured in watts per square centimeter is rising dramatically. The Pentium 4 had a power density of 46 watts/cm2, a factor of seven times the power density of the Intel486. The ratio of maximum peak power for the two machines is 20:1. The power density of a Pentium processor is already higher than a hot plate. In an often published Intel chart of power density versus process node the slope of the curve is headed toward nuclear reactor and rocket nozzle over the next five years.

The expression for power is given by:

Power = P = Pdynamic + Pstatic = Pswitching + Pshort-circuit + Pleakage + Pstatic

Power consumption has both dynamic and static components. Dynamic power consists of switching power and short circuit power. Switching power consumption results from the actively changing states of a circuit due to the charging and discharging of the effective capacitive loads. The Interconnect consumes the majority of dynamic power with clock power being the largest contributor. Switching power is given by:

Pswitching = afCeffVdd2 where
a is a measure of switching activity. Since a circuit typically does not switch every cycle, alpha can be thought of as the probability of switching

f is clock frequency

Ceff is the effective capacitance which includes any internal capacitance associated with the gate's transistors and any external capacitances, which are comprised of parasitic wire capacitance and the input capacitance associated with any downstream logic gates. This is a function of fan-out, wire length, transistor size.

Vdd is the supply voltage
Energy is defined as the integral of power over time and is not a function of frequency.

Techniques to lower switching power are combinations of reducing activity, capacitance and supply voltage. One way to reduce activity is to lower the clock frequency which impacts the performance. The best known technique for activity reduction is clock gating. Clock network power can account for as much as 75 percent of the total switching power of a chip, and sequential cells driven by clocks can account for as much as 70 percent of the total clock power. Turning off the clocks to these elements when they are not switching results in significant power savings. Using a simple AND or OR gate (depending on the edge on which flip-flops are triggered) with the enable and clock signals as
inputs produces a gated clock as output. One can also employ a level-sensitive latch to hold the enable signal from the active edge until the inactive edge of the clock.

Similarly one could employ power gating recognizing that the system or sizable blocks within the system have both active and standby modes of operations. Power could be shut off or gated to these blocks when operating in a standby mode and restored as needed. The gated circuitry would not dissipate any power when turned off. Additional circuitry would be required to monitor the need for these functional blocks. A problem with power gating is the latency between when the signal to turn a unit on arrives and when the unit is ready to operate. Retention flip-flops on an isolated power supply could be used to save the logic state of all sequential elements when a chip is powered down,
eliminating the need to reinitialize the device when it comes out of standby mode. Some products support multiple levels of standby (soft off, nap and sleep) which differ in terms of the amount of power saving and latency.

Load Capacitance can be reduced by downsizing the gates and by minimizing total wire length. Power-aware placement algorithms could minimize the length of critical wires, thereby reducing their associated parasitic capacitances. Such algorithms should weigh the amount of switching activity that is associated with each wire.

Since the switching power depends quadratically on the voltage supply, voltage scaling should be a fruitful area for power reduction. However, this also reduces the switching speed of the gate. One approach would be to partition the design into functional blocks that are fed by different voltage supplies. These are referred to as voltage islands. Performance critical functions could be located in the higher voltage domains and less critical functions in the lower voltage domains. Voltage converters or level shifters would be required between modules operating at different supply voltage levels.

Several things can be done during the very early design phases to improve the power consumption situation including algorithm development, data representation, precomputation based logic, logic restructuring, pipelining, guarded evaluation and delay balancing. Tradeoffs can be made between functional parallelism and frequency and/or voltage. A block of logic running at a given frequency with a given supply voltage could be replaced with two copies of that block. Each copy would performs half of the task while running at a lower frequency and/or using a lower voltage. Using this technique, the total power consumption of the function may be reduced. The performance is maintained but at the
expense of using more silicon area.

Pshort-circuit = IscVdd

During a transition this is a momentary short circuit current or “crowbar” current flowing between Vdd and GND when transistor stacks switch state.

Leakage Power

In the past dynamic power was the dominate factor. However, leakage power is becoming a significant issue as the industry moves to new process nodes as shown in familiar chart from Intel. The x-axis could be expressed in terms of the year.

The three primary sources of leakage current are sub-threshold (I1) or source-to-drain leakage current which grows exponential with lowering Vt and increasing temperature, reverse bias junction band-to-band tunneling current (I2), and gate oxide tunneling current (I3) which could be addressed by using high-k dielectric material. Sub-threshold leakage is dominant.

For mobile/portable devices with a high standby-to-active ratio, leakage current may be the dominant factor in determining overall battery life.

It should be noted that an off transistor stack has an order of magnitude lower threshold leakage than an individual transistor.

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-- Jack Horgan, Contributing Editor.


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