June 14, 2004
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
When I was a child my parents told me the nursery story of Goldilocks and the Three Bears. More recently I enjoyed reading the story to my grand daughters. One of the morals of the story is that 2 choices are not enough.
Companies have been forced to choose between FPGA and ASIC implementations of integrated circuits. The gulf between FPGAs and ASICs is as great as between the Poppa Bear and the Momma Bear in the story. I won't say which one is the Poppa and which is the Momma.
In relative terms ASIC development entails an enormous amount of non-recurring engineering (NRE) charges, takes a considerable amount of time and engineering talent, requires sophisticated design tools and has a significant amount of risk. There is a technological risk that the targets for performance, reliability, yield and schedule will not be met. With shrinking product lifecycles time to market is crucial to business success. Second and third to market vendors will encounter a smaller remaining available market and have less time in market to mine it. There is also a marketing risk that product requirements may change during the long development process due to shifts in end user
preferences or the actions of competitors. The lack of programmability makes it difficult to respond such changing requirements. In a series of studies Collett International Research has shown that first silicon success rate for ASICs has fallen from 48% in 2000 to 39% in 2002 to 34% in 2003. Forty percent of designs required more than one re-spin. Logic and functional flaws had the largest failure contribution rate at 45%. More than 82 percent of these flaws arose from design error in which bugs remained hidden in the design through to tapeout. With shrinking geometries mask costs and fabrication turnaround time have increased dramatically. Due to their high risk and considerable NRE
cost the number of ASIC designs has been decreasing dramatically from over 10,000 in 1998 to less than 3,500 in 2002. IC Insights reports 1,400 standard cell designs in 2003.
On the positive side the manufacturing cost per unit volume even when NRE costs are included can be very small for large volume applications such as cell phone and mobile entertainment devices. All standard cell ASICs have relatively high performance and low power consumption.
A third choice is now available, namely Structured ASICs (SA). This split-the-middle choice would be characterized by SA vendors as the “best of both worlds” or as the Baby Bear said “Just right”.
A structured ASIC typically consists of predefined logic cells and configurable memory cells in the form of an array. Each of the cells contains customizable combinatorial logic to form adders, multipliers, multiplexers, flip-flops and so forth. The mask layers required to build the logic-cell array are common to all customer designs. The logic cells are then customized and interconnected with a few metal layers on top. The SA has built in clock domains, preconfigured DFT circuits (scan, BIST), power distribution, embedded IP and so forth. This simplifies and reduces the design effort.
A structured ASIC is designed and fabricated by the vendor with the last few metal layers left undefined. The customer makes the final connections to produce a custom IC. The prefabricated wafer, also known as a master slice, is generally produced in volume and stockpiled for future customer use. This approach shares the device's development cost across multiple customers. The customers provide designs in RTL or netlist form to be mapped onto the cells. The wafer is retrieved and the upper metal layers used to implement the design.
Structured ASIC vendors really provide a service that delivers the customer's design. This generally involves third part fabrication and manufacturing (packaging, testing). The design tools used are a combination of proprietary and industry standard EDA tools.
Structured ASICs offer the performance, power consumption and unit costs associated with standard cell ASICs along with the low NRE and fast turnaround time of an FPGA. The table bellows is a qualitative comparison of the three approaches.
is possible that a particular product may pass through all three regions during its lifetime.
Several people I interviewed for this article have said that structured ASIC is still a missionary or evangelistic market. Much needs to be done by the vendors to plant the seed, educate designers and their management about the benefits of this solution. Towards this end Chip Express, Lightspeed, Synplicity, and Tera Systems announced just this past February that they have formed the “Structured ASIC Association” (SAA). The founding members are collaborating to firmly establish Structured ASICs as a unique market segment and educate the industry about this new technology. Launched by the SAA, the new Structured ASIC website
http://www.structuredasic.com) was developed to provide a comprehensive source of information about Structured ASIC technology. The SAA defines a Structured ASIC as “an integrated circuit architecture that delivers reduced entry cost and faster time to silicon using a predefined arrangement of late-stage mask-customizable logic and pre-diffused macros.” This means customers can expect low NRE, low unit pricing, and fast turnaround time for prototype and production Structured ASIC devices.
In the press release announcing its formation the SAA claims that customers using Structured ASICs reap many of the performance and cost advantages of a full custom ASIC in a device which can be fabricated in as little as three weeks. Using this revolutionary new technology, design teams can build complex ASICs for 25 percent or less of the development cost of a standard cell device, at a unit cost approximately 90 percent less than a complex FPGA.
$70 million in 2003.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Jack Horgan, EDACafe.com Contributing Editor.
Be the first to review this article