June 28, 2004
Mini DAC Review + ESL Chapter 2
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Mini DAC Review

The attendance figure I saw for DAC was around 11,000, slightly up from recent years but down from several years earlier. In a pre-DAC article I compared DAC to Comdex whose attendance had been running around 200,000 during the late nineties. Comdex attendance fell dramatically after September 11 and the dot.com implosion. The management firm went bankrupt. A new management group took over but the revised format drew only 45,000 visitors last year. This year's event has been cancelled. Next year they plan an event focused on corporate technology buyers. In explanation spokesperson said the IT industry has been splintered and fragmented and small, specialized shows have sprung up.
Against this environment for trade shows DAC has been drawing very well.

One of my favorite sayings is “Everything in life is a two edged sword”. The good news for DAC, held in San Diego June 7-11, was the tremendous amount of activity going on. The bad news was that much of it was held in parallel. Not having mastered the trick of being in multiple places at once, I missed more than I saw.

The technical conference was based on a 20% acceptance rate of nearly 800 submissions. There were tracks for Power, Physical Circuit Design, System Level Design & Verification, Logic Design & Test, Embedded Systems and Nanometer Analysis & Simulation. The printed conference proceeding was 2.5 inches thick and weighed about 5 lbs. A knapsack was provided to carry this tome and vendor collaterals. There was also a CD version. These were quality technical papers from universities and labs not puff pieces touting commercial products. On Tuesday there were several panels on Business Issues.

Throughout the show there were well attended panel sessions at the DAC Pavilion out on the exhibit floor. This was very convenient as it was quite a walk from the exhibit floor to the rooms where conference sessions were being held. There were also vendor sponsored sessions offering boxed lunches.

Walden Rhines, CEO of Mentor Graphics and current chairman of the EDA Consortium, gave one of the keynote addresses entitled “EDA Industry Growth: Are There Enough New Problems to Solve?” And parenthetically “that people will pay for”. He contends that most EDA revenues come from major new design methodologies. He identified DFM, RET, Parasitic Extraction and IC Layout Verification that as a group had grown from $200 million to $500 million in five years. He projects that this revenue will exceed $2 billion by 2010. He describes RET as the first wave of DFM. The reason for interest in DFM include enormous cost savings for semiconductor manufactures, extended
life of photolithographic
equipment, and the need for yield enhancement at sub-100 nm feature sizes. He also identified ESL and FPGA as opportunities for considerable growth.

Pat Gelsinger, SVP & CTO of Intel, gave the other keynote address on “Giga-scale Integration for Tera-Os Performance”. He sees major challenges due to statistical fluctuations that produce static and dynamic variations. Static variations occur during manufacturing, so that all chips do not have the same characteristics but a rather a distribution, e.g. some faster, some slower, some leaky and some less leaky. An example of dynamic or run time variations would be hot spots. Scaled devices act statistically. Consequently we need a new way of thinking about chip design. We must believe that transistors are free, shift our thinking from deterministic to probabilistic and from
single to
multiple variable optimization, and move from local to global optimization. He compared the situation to the shift from Newtonian physics to quantum physics.

Note: Videos of both keynotes are accessible on

The CEO Panel on EDA: This is Serious Business” featured Walden Rhines of Mentor Graphics, Aart de Geus of Synopsys and Mike Fister of Cadence. Mike is the new CEO at Cadence and in lieu of PowerPoint slides invited everyone to the booth. He said "I'm excited about it for Cadence and the industry, but the barriers ahead are real and almost beyond comprehension of the human dynamic". Rhines pointed out that while the EDA industry, which consists of three major vendors and 300 much smaller ones, could be segmented into fifty different submarkets, each one is dominated by a single vendor. He said that Mentor wants to play only in those areas it can take and hold a leadership
This sounds much like Jack Welsh's philosophy at General Electric. Mentor's R&D investments and acquisition strategy are based upon this view. Aart de Geus noted that as silicon becomes more complex, with implications for yield, chip manufacturers must work more closely with EDA vendors. Each CEO pledged allegiance to open standards and interoperability.

Three acquisitions were announced at DAC: Synchronicity by MatrixOne, Hier Design by Xilinx and 0-In Design Automation by Mentor Graphics. The MatrixOne acquisition of Synchronicity was covered in last week's editorial.

Xilinx Inc acquired FPGA floor planning vendor Hier Design Inc. for an undisclosed amount. Hier was founded in August 2001. In March 2003 the firm had announced $6.2 million in venture funding, including equity investments from Xilinx Inc and Cadence Design Systems Inc. Hier's PlanAhead hierarchical floorplanner software is the heart of its silicon virtual prototyping solution for high-end FPGAs. PlanAhead provides a hierarchical, block-based and incremental design methodology. With PlanAhead, designers can group critical paths and modules to increase routability through connectivity analysis and utilization control. PlanAhead also provides manual or automatic partitioning, manual or
automatic physical block sizing and placement along with clock I/O and clock region planning. In early May Hier announced the availability of TimeAhead, a static timing analysis environment.

Mentor Graphics Corp. announced it has agreed to purchase 0-In Design Automation (pronounced "zero-in") for an undisclosed sum. Revenue figures for 0-In Design Automation were not available; however it was acknowledged that the company had not reached profitability. Mentor will integrate 0-In's tools for assertion and structural coverage into its Scalable Verification platform. 0-In Design Automation's Archer-CDV supports a coverage-driven verification flow in which metrics are used to gauge the effectiveness of each step in the test plan and to determine which areas of the design need more verification effort. Archer-SF provides support for automatic design checks and user-specified
assertions that can be analyzed using formal static verification engines. CheckerWare are protocol monitors coded in Verilog that capture and check the complete set of cycle-by-cycle protocol rules for complex standard buses and interfaces.

ESL Chapter 2

In mid-April I wrote an editorial entitled
ESL Chapter 1. At the end of the article I threatened to do a second chapter. The following week I wrote an editorial on
Behavioral Synthesis that had a section on SystemC which is closely related to ESL. This week I am following through on my threat.

On Sunday and again on Monday in the DAC Pavillion Gary Smith, chief EDA analyst at Gartner Dataquest, gave a presentation on EDA Business Forecast. In particular he showed a chart on the ESL revenue from 1992 with projections through 2007. According to the data, the first generation of ESL came in 1992, and produced about $23 million in revenues. The second generation came in 1996 and increased revenues to $41 million. Revenues peaked at $104 million in 1998 and then declined. Gary blames some lack of success on the overselling of ESL into the wrong applications.

Figure 1 ESL History

Based upon data from Gary Smith Gartner-Dataquest

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-- Jack Horgan, EDACafe.com Contributing Editor.


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