November 01, 2004
More Assertions
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


This week's editorial follows up last week's on Assertion Based Verification (ABV) by including @HDL another vendor focused on this important area and also relevant product announcements by Cadence and Mentor Graphics. In addition this editorial presents updates on Intel and Google that were subjects of previous editorials.

@HDL Incorporated

@HDL was founded in April 1999 by Badruddin Agarwala, Vivek Bhat, and Tarak Parikh, former founders of Frontline Design Automation, a Verilog simulation company acquired by Avant! in 1997, and Yusuf Attarwala from SGI. @HDL is a privately-held company that received first round funding in early 2000. Investors and board members include Dr. Prabhu Goel former founder and CEO of Gateway Design Automation Corporation, and S. Atiq Raza, former President and COO at AMD.
The firm is a founding member of PSL/Sugar Consortium that promotes the use of PSL within the industry.

@HDL is pioneering the use of Adaptive Functional Verification (AFV) technology that combines the formal and simulation approaches with SOC/system-level design analysis and debugging. Adaptive Functional Verification is the selective, automatic application of formal model checking and dynamic simulation algorithms based on the property and complexity of the RTL code comprising the IP blocks and SOC.

“An adaptive approach that uses automatic formal model checking along with intelligent-random simulation, and high-level RTL analysis/debugging can dramatically improve verification times and shorten the overall cycle. In short, designers need an "Intelligent RTL Testbench" methodology that fully automates the verification flow for complex SOCs.”

In May 2003 @HDL announced it had licensed IBM's premium RuleBase formal verification technology offering high-performance static analysis of very large chip designs. This technology had been developed at IBM Haifa Research Labs.

In November 2003 @HDL introduced major update to its family of functional verification solutions. The Assertion Studio technology had five major components.
Visualizer reads in assertions written in either PSL or SV and automatically
creates the equivalent timing diagram for the assertion sequence.

Interpreter verifies assertions and assertion fixes by directly applying the PSL or SV assertion on simulation waveform data without having to re-run the edited assertion either formally or through simulation.

Explorer helps determine why a violation occurred during simulation or formal model checking by generating waveforms that show the sequence of events leading up to the violation and decomposing a complex PSL or SV assertion into its constituent sub-expressions and detailing precisely which part of the assertion was violated.

Assessor reports whether or not certain transactions occurred during simulation. A query language mechanism makes it easier for the user to find out exactly which transactions occurred and when. Coverage metrics are also available to measure design activity during simulation and to complement other metrics such as code coverage and testbench functional coverage.

Engine technology takes the user-written assertions in PSL or SV and outputs simulate-able and synthesizable Verilog to allow smooth interoperability immediately.
The @HDL product line consists of two tools, @Verifier and @Designer that form the basis of the company's AFV solution. @Verifier finds RTL bugs earlier in the design cycle by using formal model checking to verify automatically generated or user-written assertion. @Verifier automatically identifies design constructs like FIFOs and FSMs and generates assertions to check for common problems including one-hot drivers and decoders, parallel and full case statements, unreachable and terminal state, never reachable conditions and codes, FIFO read/write and reset errors, index-out-of range, and stuck at zero/one. Automatically generated assertions can be verified formally, or written out in
SystemVerilog or PSL for use in simulation. @Verifier-ZX combines @Verifier's ease-of-use with IBM's RuleBase solver technology. @Verifier-DP runs multiple assertions in parallel, leveraging existing server farms to achieve linear speed improvement. @Verifier Multiple Clock Domain Verification/Analysis (MCDVA) automatically identifies master clocks, clock tree, clock domain crossing and synchronizers. The module provides both structural and functional domain verification. @Designer delivers graphical debugging and design analysis environment to isolate functional errors during creation, formal model checking, simulation, and synthesis of Verilog-based designs. The module offers source
code debugging, memory viewer and waveform viewer. Pricing is around $150,000 for a three year license.

@HDL lists among its customers SiNett, Raza Foundries, Onnotech (Toshiba), Fujitsu Labs America, MegaChips, Oki Semiconducror and AMD. @HDL is a member of the Cadence Connections Program, the Mentor Graphics) Value Added Partners program and the Synopsys in-Sync Program.

I spoke with Tarak Parith the VP of Product at @HDL. He said that the privately held company has about thirty customers and 15 to 20 employees. The firm employs a direct sales force and a rep in Japan. Tarak believes that formal verification is still a missionary sale. It is difficult to crystallize benefits for prospects. He sees the challenges facing more rapid adoption are the relatively new languages that must be learned, the lack of useable tools and the performance impact on simulation execution. Formal verification is not for everyone. While basics assertions are simple and straightforward to compose, expressing complex behavior can be difficult without proper training, support
and tools. Rather than attempting to use formal verification everywhere, he recommends having a dedicated, knowledgeable team focused on problem areas. Tools are required to constrain the design to limit unrealistic failures and to analyze the cause of assertion failure. On the other hand he sees automated assertion generation becoming commonplace.

On October 18th Cadence announced a comprehensive assertion-based verification (ABV) solution as a part of its Incisive functional verification platform. The solution speeds verification of complex designs by creating an environment that helps users define assertions correctly, enables early detection of bugs close to the source, and monitors for completeness through assertion coverage. This functionality has been integrated into the platform's Incisive Unified Simulator. It includes broad, native assertion support for Property Specification Language (PSL), SystemVerilog Assertions (SVA) and Open Verification Library (OVL). In addition to these Accellera standards, Cadence is also
introducing an extended open-source library of assertions. This Library incorporates 50 complex assertion statements and code for customization. This library will be available in both PSL and SVA languages. A sample set of library elements is posted on the web and available for review.

On October 11th Mentor Graphics announced key extensions to its Scalable Verification solution with a new version of its ModelSim simulator and advanced verification technology from the recently completed acquisition of 0-In Design Automation.

With the ModelSim 6.0 simulator and the 0-In product line, Mentor Graphics now offers standards-based support for the most advanced verification methodologies, the press release said. Offering support for assertion-based verification and coverage-driven verification flows, as well as verification IP, the Scalable Verification platform offers engineers a faster way to reach verification closure than current methods.

According to Robert Hum, VP and GM for Mentor's Design Verification and Test Division, existing verification methodologies have run out of steam. "Designers are looking for new solutions that can dramatically increase their productivity. Methodologies and tools like assertions, static analysis, functional coverage, and coverage-driven verification are required to close the verification gap."

On Oct. 12, 2004 Intel Corporation announced its results for the third-quarter. Total revenue of $8.5 billion was up 5% sequentially and up 8% year-over-year. Third-quarter net income was $1.9 billion, up 8% sequentially and up 15% year-over-year.

The gross margin percentage for the quarter was 55.7 percent, as compared to the revised expectation of approximately 58 percent, plus or minus a couple of points, primarily due to higher than expected inventory reserves; higher than expected motherboard and chipset units and lower than expected processor units in the revenue mix; and an inventory write-down as a result of lower chipset unit costs.

The effective tax rate for the quarter was 21.4 percent, lower than the July expectation of approximately 31 percent and below the September expectation of approximately 29.5 percent. The September expectation reflected the impact of a higher percentage of profits being generated in lower-tax jurisdictions.

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-- Jack Horgan, Contributing Editor.

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