June 06, 2005
Mentor's Questa Verification Products
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On May 16, 2005 Mentor announced its new line of Questa verification products. The Questa verification products offer built-in support for testbench automation, coverage-driven verification (CDV), assertion-based verification (ABV), and transaction-level modeling (TLM). This initial release includes two new products: Questa SystemVerilog and Questa Advanced Functional Verification.
I had an opportunity to discuss these products at length with Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division.
bugs. The indication there is that no amount of tool optimization is really going to help. You need a change in methodology.
Given the consequence of functional bugs in terms of the cost of re-spins and the opportunity costs in terms of longer time to market (TTM), it is not surprising that a number of new approaches are being tried to have an impact on bugs. These include assertion based verification, functional coverage, constrained-random testing, dynamic-formal verification, transaction-level verification etc etc. There are lots of different ways of coming at the problem. The question is whether all of these methodologies will be used, whether one particular methodology will dominate or how this whole thing will turn out.
Verification as we practice it today is basically test benches, some sort of an executable model of your product and a simulator. That's today's dominate methodology. That methodology is no longer powerful enough to take some of these new methods, create tools around them and create flows around them and come at verification from that point of view. Methodology shifts require change. The EDA industry has to react and designers have to react.
Robert stressed the importance of standards as an enabler for driving methodological change. Standards really help change the rules. Wherever you have standards the industry can move forward much more quickly. It was really when Verilog was standardized and entered the public domain that the market really took off for natural languages and RTL design. One thing I think we're sensitive to is that to the extent that something can be standardized and that all vendors have access to it, can cause a methodology to preferentially take off.
We have taken SystemVerilog which is a standard we believe that the industry is willing to adopt. We have created an implementation of SystemVerilog that embodies a powerful simulation engine which is based upon ModelSim. We have included assertions based verification both with PSL and with SystemVerilog. We have coverage driven verification with some Verilog native coverage directives and things like that. And we have a transaction modeling approach that permeates the way that our graphical user interface works.
The table below shows the features of the three verification products.
The standard ModelSim product has in it Verilog, Verilog 2001 and VHDL. But if you buy that product you don't get assertion and you don't get testbench automation. Quest SystemVerilog has all the SystemVerilog stuff in it and Quest AVS has not only SystemVerilog in it but PSL and System C. It is the highest priced product that we have. There are upgrade paths if you already have ModelSim and want to do SystemVerilog. You can buy an upgrade.
Will ModelSim go away at some point?
view ModelSim is the product we've developed and will support until people stop buying it.
want to use e in a VCF environment, that has to be done through a PLI link and it slows everything down.
What percent of the 140,000 ModelSim users use SystemVerilog?
That's really hard for us to say because of the way we package ModelSim. We have packages where you can use either Verilog or VHDL and we have other packages available where you can use Verilog and VHDL. We have not been able to successfully breakout the statistics of what people run. It is true to say from a national point of view that VHDL usage is not growing. It is also true that more VHDL users are importing Verilog modules. So if you have a pure VHDL design you might be importing something that comes from a Verilog design. Most of what we have seen is that pure VHDL has been mostly replaced by mixed language. Most of what we sell now is mixed language.
The trend seems to be that VHDL community is not growing. That does not imply that it is shrinking but it is just that we haven't seen growth in this area. We do not see customers adopting it but there are lots of VHDL users that are integrating bits and pieces of SystemVerilog.
you debug the assertions? You can't debug them in a normal simulator GUI because that only has waveforms. So inside the GUI we now have an assertion debugger and a bunch of support to really help people be productive with whatever language they want to use.
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-- Jack Horgan, EDACafe.com Contributing Editor.
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