June 06, 2005
Mentor's Questa Verification Products
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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On May 16, 2005 Mentor announced its new line of Questa verification products. The Questa verification products offer built-in support for testbench automation, coverage-driven verification (CDV), assertion-based verification (ABV), and transaction-level modeling (TLM). This initial release includes two new products: Questa SystemVerilog and Questa Advanced Functional Verification.

I had an opportunity to discuss these products at length with Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division.

Whenever a new product is introduced I am always interested in what problem it is trying to solve. Robert referenced the well known 2002 study by Collet International Research which surveyed users about their design processes. In particular it tracked the causes of IC/ASIC mask re-spins. The survey found that the leading factor was logic/functional flaws. They occurred in 71% of the cases. The second biggest factor, clocking, occurred in just over 20%. In fact a 2004 study by the same firm showed that functional errors were even a larger factor. In some sense this is really counter intuitive because you are talking about 40 million or 50 million gate design. One would expect that at this fine geometries, you would get crosstalk or some weird analog effect, parasitics or something like that would cause the chip not to work but the overwhelming complexity and amount of logic on these chips still makes it true that logical or functional errors are still the ones that are the singly largest category. Robert also shared a slide from Intel published at DAC 2003 which showed the number of bugs found for each generation of the Pentium. The graph was a straight line on a semilog plot. The bug count correlated well with the number of transistors. Clearly whatever is happening in terms of design methodology and tools is not having an impact on reducing the total number of
bugs. The indication there is that no amount of tool optimization is really going to help. You need a change in methodology.

Given the consequence of functional bugs in terms of the cost of re-spins and the opportunity costs in terms of longer time to market (TTM), it is not surprising that a number of new approaches are being tried to have an impact on bugs. These include assertion based verification, functional coverage, constrained-random testing, dynamic-formal verification, transaction-level verification etc etc. There are lots of different ways of coming at the problem. The question is whether all of these methodologies will be used, whether one particular methodology will dominate or how this whole thing will turn out.

Verification as we practice it today is basically test benches, some sort of an executable model of your product and a simulator. That's today's dominate methodology. That methodology is no longer powerful enough to take some of these new methods, create tools around them and create flows around them and come at verification from that point of view. Methodology shifts require change. The EDA industry has to react and designers have to react.

Robert stressed the importance of standards as an enabler for driving methodological change. Standards really help change the rules. Wherever you have standards the industry can move forward much more quickly. It was really when Verilog was standardized and entered the public domain that the market really took off for natural languages and RTL design. One thing I think we're sensitive to is that to the extent that something can be standardized and that all vendors have access to it, can cause a methodology to preferentially take off.

We have taken SystemVerilog which is a standard we believe that the industry is willing to adopt. We have created an implementation of SystemVerilog that embodies a powerful simulation engine which is based upon ModelSim. We have included assertions based verification both with PSL and with SystemVerilog. We have coverage driven verification with some Verilog native coverage directives and things like that. And we have a transaction modeling approach that permeates the way that our graphical user interface works.

The table below shows the features of the three verification products.
The standard ModelSim product has in it Verilog, Verilog 2001 and VHDL. But if you buy that product you don't get assertion and you don't get testbench automation. Quest SystemVerilog has all the SystemVerilog stuff in it and Quest AVS has not only SystemVerilog in it but PSL and System C. It is the highest priced product that we have. There are upgrade paths if you already have ModelSim and want to do SystemVerilog. You can buy an upgrade.

Will ModelSim go away at some point?

ModelSim is the most popular simulator in the market. There are over 140,000 licenses out there. ModelSim itself is not going to go away as long as VHDL and Verilog remain in use. When we talk about the industry transitioning to SystemVerilog, of course this will not happen overnight. A large portion of the population will continue to use ModelSim as it is. As people convert over they get the benefit of having SystemVerilog available plus the benefit of having assertion based verification and testbench support in there. I think the conversion in the industry will happen quickly over the next three years. You will see rapid adoption of the SystemVerilog environment. From our point of
view ModelSim is the product we've developed and will support until people stop buying it.

Because of the architecture of what we have, ModelSim in a sense is continuously supported because the simulator is a single kernel the ModelSim kernel. ModelSim is itself the real guts, it does the execution. We created from scratch the constraint solver which is the heart of the directed random testbench. Functional coverage is the module that collects all the functions and coverage and presents them. This single kernel environment executes Verilog, VHDL, SystemVerilog and System C; all one nice environment tied together. This makes it easy for us to support and maintain. It's standards based. It gives higher performance than if you have separate architecture. If you use e and
want to use e in a VCF environment, that has to be done through a PLI link and it slows everything down.

What percent of the 140,000 ModelSim users use SystemVerilog?

That's really hard for us to say because of the way we package ModelSim. We have packages where you can use either Verilog or VHDL and we have other packages available where you can use Verilog and VHDL. We have not been able to successfully breakout the statistics of what people run. It is true to say from a national point of view that VHDL usage is not growing. It is also true that more VHDL users are importing Verilog modules. So if you have a pure VHDL design you might be importing something that comes from a Verilog design. Most of what we have seen is that pure VHDL has been mostly replaced by mixed language. Most of what we sell now is mixed language.

The trend seems to be that VHDL community is not growing. That does not imply that it is shrinking but it is just that we haven't seen growth in this area. We do not see customers adopting it but there are lots of VHDL users that are integrating bits and pieces of SystemVerilog.

When you are faced with debugging your design of 40 or 50 million gates, one of the problems is: Where do you start looking? If you find a problem, how do you narrow down to where the bug is and how do you solve this particular problem? ModelSim has its own GUI and has had it for years. It is one of its strength. What we've done is added debug and analysis. We've added transaction to it, coverage, a whole lot of things. This new GUI will add lots of productivity. People find that if you're using PSL standalone and you are writing assertions, the assertions themselves sometimes have bugs in them. The question is: How do
you debug the assertions? You can't debug them in a normal simulator GUI because that only has waveforms. So inside the GUI we now have an assertion debugger and a bunch of support to really help people be productive with whatever language they want to use.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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