August 08, 2005
What Will My Chip Cost?
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


“What will my chip cost?” is a question whose answer that should be of great interest. An accurate estimation early in the design flow should be quite valuable when changes are easily made before considerable time, dollars and resources have been invested. Giga Scale IC is a firm that offers a tool called InCyte that attempts to answer this and related questions. Moreover a version of this product is available for free downloading from the web.

I had an opportunity to interview Adam Traidman, President and VP of Business Development at Giga Scale IC. Prior to joining Giga Scale, he ran North America West sales at Hier Design. Previously, Traidman has served in various management and technical roles at Adaptec, Monterey Design Systems, Texas Instruments, and the NASA Jet Propulsion Laboratory

What attracted you to Giga Scale?

It was really the uniqueness of the technology. This company happens to be funded by the same lead venture capital firm that funded the last company that I worked for, Hier Design, which was acquired by Xilinx in June of last year. But what attracted me to Giga Scale irrespective of that other relationship was the unique technology. Having a background in ASIC design, specifically ASIC physical design, I was well aware of the frustration that the typical designer and design manager goes through when they are trying to accomplish a number of things that InCyte helps with. First of all, the main thing is the early estimation of die size and power consumption. Very early in the design flow it is often very difficult to quantify and to use that information to your advantage to help choose between different process variants, different IP libraries, and different IP options. It was something I personally struggled with for months in wrestling with all the technical and economic tradeoffs between different options. When I saw that the tool was in this solution space, a tool that could help you make the decisions accurately very early in the flow, it appealed to me greatly from a technology perspective. In terms of market perspective, the InCyte product is also very unique. There really hasn't been any mainstream EDA company in this space- what we call the early
architectural exploration and estimation space. It just seems like an area under served by EDA so far. So it was a unique product which I happened to believe in based upon my technical background and also in the context of the market it was a unique space. It felt like a good opportunity.

On the company website George Janack is listed the founder and executive chairman. You are the president. Who is in charge of day-to-day operations?

I'm in charge of operations. George is also the CEO at Silicon Navigator. I fill that responsibility here.

Any challenges with the founder still actively in the picture?

It's a sign of a strong leader when you realize that you've grown a company or a concept to the point when from a day-to-day perspective can be run by someone who can execute on the vision that you initially laid out. There are all sorts of entrepreneurs. There are the technical visionaries, the technologists who come up with the fantastic new product ideas, like to found companies and move on to the next one. They are those who take it all the way to exiting or going public. George fits someway in between. He is a fantastic technical visionary, literally a genius. I can honestly say that he is a brilliant engineer. His passion is the technology and the capacity he plays at Giga
Scale is precisely where he can be the technical and business visionary. He is the sounding board for ideas, a strategist and sort of high level system architect. One of his strengths is that he recognizes when the technology has been sufficiently developed to a point where it makes more sense to bring in a team of people around him to execute the initial vision he laid out and then do what he does best which is to focus on long term vision and long term strategy.

What is Giga Scale IC's mission?

Giga Scale's mission as a design automation company is to be best in class to produce what we call IC estimation and architectural analysis tools. As I mentioned before this is a very unique space, one you won't find any larger or even smaller EDA companies playing in. The goal of course as it is with most design automation tools is to lower chip costs but still meet functional and performance goals. The company is just over two years old and based in Cupertino, CA. We are venture capital backed. As of today we have more than 2,000 seats of the InCyte tool.

Does this number include paid and unpaid licenses?

The current number of users is about 2,300. That figure includes folk who have downloaded the free version of the tool as well as those who have upgraded to subscription version and those who are enterprise customers. The figure includes both free and paid customers.

In December 2003 there was a press announcement of a $1.2 million investment round led by ITU Ventures. Was this the total investment in the company to date?

ITU was the lead investor. There are also a number of angel investors. The total that has been invested is a little higher than that.

Would you give me a high level overview of the product?

There are two main components. Fast and accurate chip estimation. A user will typically use the tool by defining their chip specification in the software. This spec is a high level description of their chip. From that InCyte estimates the die size, yield, chip costs as well as power consumption and leakage. When we talk about chip cost, we are talking about comprehensive economic analysis. We are utilizing defect density data, wafer pricing data as well as package pricing data. The InCyte tool can essentially give you a complete budgetary quote for a finalized state which means in addition to the quote estimation we can give you a complete cost estimation of the final packaged chip.
This economic analysis capability was just released prior to DAC.

Once the chip specification is in InCyte for some users what is more important than even the initial estimation is what we call architectural exploration. Users have the ability to trade off what their design would look like in the context of different manufacturing and IP options, something macro like switching from 130 nm to 90 nm or switching a process variant by switching to LV-LowK or different IP libraries like Artisan high performance versus high density standard cell. The important thing if you make these tradeoffs is that you can quantify the impact that they have on the metrics that InCyte calculates such as die size and power consumption. The goal here is to let the design
teams explore which of the different options will allow them to meet whichever goals are important as well as expose the interaction between all these metrics.

Why this product now?

One of the reasons we think that the market is ripe for this type of functionality and this type of tool at the moment is what we are calling the paradigm of design for cost. In the high volume, low margin world such as cell phones, price pressure on the final products are effectively pushing down the cost of all the components within those products including the main ICs which contribute highly to the cost. That cost sensitivity is trickling from the end user buying the cell phone all the way down the semiconductor supply chain literally to the desk of the IC designer. The design teams are being asked very early in the flow to calculate how much the chip will cost
and to use that cost number as input to the design flow. The trouble is that the design teams are struggling to figure out what the costs will be and how the technical decisions will impact those costs because of a lack of architectural analysis tools. There are literally dozens of manufacturing options at 90 nm and 130 nm and hundreds of IP libraries. It is unclear which combinations are optimal.

1 | 2 | 3 | 4 | 5  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, Contributing Editor.

Review Article Be the first to review this article
CST Webinar Series


Featured Video
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
SEMICON Europe at Grenoble France - Oct 25 - 27, 2016
ARM TechCon 2016 at Santa Clara Convention Center Santa Clara CA - Oct 25 - 27, 2016
Call For Proposals Now Open! at Santa Clara Convention Center, Santa Clara, CA California CA - Oct 25 - 27, 2016
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy