Mentor Verification Horizons: Online UVM/OVM Methodology Cookbook


Our first article this month came out of a discussion I had with a colleague at DVCon earlier this year. He was looking for some ideas on how to justify an investment in “methodology” to his management team who, of course, were not as steeped in these ideas as many of us are. The resulting questions and answers will hopefully serve to remind all of us of the “ First Principles ” behind the technologies, techniques and tools that we’ve come to rely on to verify our ever more complex designs.

We next introduce you to the Online UVM/OVM Methodology Cookbook, a new online resource from our Verification Academy available in the New UVM/OVM portal. The biggest problem with methodology textbooks is that they often become out of date as soon as they are published. We published online to mitigate that risk and commit to update the Cookbook as the Universal Verification Methodology (UVM) from Accellera evolves. Evolution is inevitable as users and vendors explore features in UVM, and the Cookbook will be a great way for you to keep informed. This particular article is the overview page for the new UVM register modeling facility . In it, you’ll see a high-level explanation of the functionality along with links to other more in-depth discussions of specific pieces of the package, a format used throughout the Cookbook.

Our next article is the conclusion of Hans van der Schoot’s “ A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches ,” which we started in the previous issue. Part two takes us through the mechanics of implementing the transaction-level interface between simulation and emulation.

With the recent announcement of our Questa Ultra platform, we continue to enhance our Intelligent Testbench Automationcapability. In “ Combining Algebraic Constraints with Graph-Based Intelligent Testbench Automation ,” you’ll see how the addition of algebraic constraints enhances the Questa inFact stimulus generation by simplifying the stimulus definition.

In " Data Management: Is There Such Thing as an Optimized Unified Coverage Database ?" my colleagues Darron May and Gabriel Chidolue provide an overview of the Unified Coverage Database (UCDB), which provides a platform for the collection and analysis of coverage data from multiple tools and verification engines. I think you’ll see why the UCDB was chosen by Accellera as the basis for the upcoming Unified Coverage Interoperability Standard (UCIS).

We have four articles in our "Partners' Corner" this issue. The first, " A Unified Verification Flow Using Assertion Synthesis Technology ," written in conjunction with our friends at NextOp, shows how their Bugscope assertion synthesis tool can be integrated into a unified verification flow with Questa and Veloce. In “ Benchmarking Functional Verification ,” Test and Verification Solutions expand on the Functional Verification Capability Maturity Model, which helps you measure the maturity of your verification process and provides a framework for planning improvements. Putting standards into practice, HDL Design House next shares their experience in creating “ UVM-Based SystemVerilog Testbenches for VITAL Models .” Find out the “four Cs” of reusability and how they’ve used UVM to create a family of testbenches for VITAL models while minimizing the amount of code they needed to write. We round out the Partners’ Corner with “ Efficient Failure Triage with Automated Debug: a Case Study ” from our partners at Vennsa Technologies.

We close this issue with a special treat. We are reprinting a copy of “ Are Macros in OVM & UVM Evil? – A Cost-Benefit Analysis .” This paper won the Best Paper award at DVCon back in March, and we wanted to make sure that you saw it. Without giving away the ending, the answer is “yes.” You’ll find a great explanation of why, and which macros are OK to use.

I hope you enjoy this issue.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons

Review Article Be the first to review this article
Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy