HENDERSON, Nev. — (BUSINESS WIRE) — May 23, 2011 — Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, enhances HES™ (Hardware Emulation Solutions) by expanding its debugging capabilities, ASIC gate capacity and speed of operation.
The new release of HES Design Verification Manager software, DVM™ 2011.04, supports SCE-MI 2.0 standard and provides 4 MHz emulation speed for designs with 10 million ASIC gates. The new version of DVM automates the entire design setup process, including the insertion of SCE-MI transactors into the user’s design and SCE-MI API functions to interface with the C/C++ model or testbench on the software side.
Significant improvements in dynamic debugging have also been implemented to provide full visibility into the design, visualization of results in a waveform viewer, setup of hardware breakpoints and triggers, and memory viewer/editor.
“Our key objective is to meet the demands of hardware and software teams to co-verify target applications, drivers and OS with the RTL subsystem at multi-MHz speed with extensive debugging capabilities,” said Mr. Zbyszek Zalewski, General Manager of Aldec’s Hardware Division.
Learn more about the new enhancements to HES at DAC 2011, Booth# 1243. Aldec registration is available at http://www.aldec.com/dac48.
HES is a complete hardware-based verification solution for large and complex SoC/ASIC designs that provides a unified platform for simulation acceleration, transaction level emulation, HW/SW co-verification, software validation, virtual modeling and prototyping. HES includes Transaction Level Modeling (TLM) with SCE-MI 2.0 for high-performance emulation using FPGA-based prototyping boards from Aldec, Dini Group™, Synopsys™ HAPS™ or custom in-house boards with tens of millions of ASIC gates. Additional information about HES is available at http://www.aldec.com/hes.
Design Verification Manager (DVM) is the software component of HES that facilitates easy design setup, automatic design partitioning, automated conversion of multiple ASIC clock domains to single FPGA clocks and high speed signal multiplexing for FPGA interconnections. DVM provides extensive debugging capabilities such as dynamic debugging with full visibility, ability to setup static probes, setup breakpoints and triggers, includes start, stop and step emulation controls, and memory viewer/editor.
Aldec, Inc., a 25-year EDA tool provider is committed to delivering high-performance, HDL and hardware-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.
HES and DVM are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Christina Toole, 702-990-4400