NetLogic Microsystems selects Helic’s tools for RF IC design flow

SAN FRANCISCO, CA  May 19th, 2011 — Helic, Inc., the technology leader in EDA solutions for RF and high-speed IC design proudly announces that NetLogic Microsystems selected Helic’s VeloceRF™ and VeloceRaptor/X™ to be part of their RFIC design flow.

To meet the demands of RF and high-speed design in advanced silicon processes, VeloceRF™ features a unique component-synthesis engine that generates DRC and DFM-correct inductive devices according to designer specifications. VeloceRF™ brings a complete solution for achieving an optimal floorplan, enabling silicon area reduction by optimizing inductor sizes. The tool de-risks the design from electromagnetic effects, incorporating EM coupling parasitics in post-layout simulation. VeloceRaptor/X™ is a breakthrough RLCK modeling tool with unparalleled capacity and speed suitable for integrated passives such as transmission lines, interconnects, digital high-speed lines, spiral inductive devices and MIM/MOM capacitors.

Stefanos Sidiropoulos, Vice President of Physical Layer Products at NetLogic Microsystems said that “Helic’s VeloceRF™ brings the most advanced inductor synthesis capabilities, significantly enhancing our RFIC design flow while VeloceRaptor/X™ offers high-speed and accurate electromagnetic analysis assisting our engineers in de-risking our multi-GHz designs”.

 “NetLogic Microsystems, the leader in PHY solutions for 10-Gigabit to 100-Gigabit Ethernet applications, leverages our technology to meet the challenges of multi-gigahertz nanometer scale designs and we are very proud to contribute with our tools”, said Yorgos Koutsoyannopoulos, CEO of Helic.

About Helic

 Helic, Inc. develops disruptive EDA technologies for RFIC and high-speed SoC design. We provide our customers with a comprehensive offering combining design tools, silicon IP and applications support, greatly reducing the development cycles of chips for wireless communications, broadband networking, PCs, tablets and other segments. We provide technology for rapid electromagnetics modeling, RF component synthesis, and signal integrity of silicon ICs and Systems-in-Package. Our solutions have been adopted by several major semiconductor companies since 2000. Helic is headquartered at 101 Montgomery Street, suite 2650, San Francisco, CA 94104. For additional information please visit www.helic.com.

Press Contact:

Nikolas Provatas
T: +1-866-994 3542
E: Email Contact



Read the complete story ...


Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Staff Software Engineer - (170059) for brocade at San Jose, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy