“Studying Clock Recovery Performance using IBIS-AMI Models” Available for Download

Maynard, MA – March 21, 2011 - Signal Integrity Software, Inc. (SiSoft™) today announced the availability of  “Studying Clock Recovery Performance Using IBIS-AMI Models”, a paper co-authored by Barry Katz, SiSoft President and CTO, and Dr. Michael Steinberger, SiSoft Lead Architect for Serial Channel Products.  The paper, presented at DesignCon 2011, introduces a method for extracting the jitter transfer function, jitter tolerance and pattern dependent jitter from an IBIS-AMI model under realistic channel conditions, presenting examples from a generic bang-bang clock recovery circuit and several commercial SerDes designs.

Download “Studying Clock Recovery Performance using IBIS-AMI Models” now.

A collection of resources for high-speed system designers including technical papers, app notes, webinars, videos and demos can be found at http://www.sisoft.com/elearning/.

 

###

Contact:        
Ronda Ivey Katz
Dir. of Marketing and Communications
SiSoft
(978) 461-0449, x15
Email Contact




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs


Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Upcoming Events
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Verific: SystemVerilog & VHDL Parsers
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy