Analog Bits, the Integrated Clocking and Interface IP leader, today unveiled an application specific Display SerDes (Serializer/Deserializer) IP that reduces area by up to 25 times, die-costs up to 25% and power consumption by 700mW. The new IP is silicon-proven and available immediately.

The Analog Bits Display SerDes is designed specifically for next generation flat panel displays, integrating a low power macro with a fine resolution, low jitter video clock to drive new video standards such as V-by-One HS®.

Analog Bits has achieved these technology milestones by customizing the IP's analog macro to market specifications. The Display SerDes can now be successfully ported to 90nm 65nm and 40nm designs.

"Our clocking and interconnect products have long held a reputation for high quality - especially in video," commented Mahesh Tirupattur, Executive VP of Analog Bits. "Integrating our new low-power, high-bandwidth SerDes has resulted in a compelling solution for this growing market."

For information about Analog Bits Display SerDes, please visit our website.

Founded in 1995, Analog Bits, Inc. is the leading supplier of integrated timing and interconnect IP. Products include precision clocking macros such as PLL's & DLL's, programmable interconnects such as multi-protocol SERDES/PMA and programmable I/O's as well as specialized memories such as high-speed SRAMs and T-CAMs. With billions of IP fabricated in customer silicon from 0.35-micron to 28-nanometer processes, Analog Bits has the heritage of "first time working silicon" at merchant foundries and IDMs.