Apache Design Solutions - March 2011

 Apache Spotlight

Next Generation Chip Power Model (CPM™) for Broader Range of Applications

Apache released CPM v2.0, its next generation Chip Power Model for true co-analysis/co-optimization of the chip, package, and system. Ideal for wireless and automotive markets, including 3D IC and SiP designs, CPM v2.0 expands the range of coverage to include system resonance awareness, the power transition impact on a global power delivery network (PDN), thermal co-analysis, EMI and EMC validation. It also delivers user configurable models for an effective Chip-Package-System (CPS) flow.

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 PathFinder™ Named EDN Innovation Award Finalist

PathFinder, the industry’s first comprehensive electro-static discharge (ESD) physical integrity solution, was named a finalist in the EDN Innovation Awards’ EDA Tools and ASIC Technologies category.

The EDN Innovation Award winners are selected from the finalists by a combination of EDN reader and editorial staff votes. Online voting is now open until March 31, 2011. Winners will be announced at the annual EDN Innovation Awards ceremony on May 2, 2011, in San Jose, California.

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 GlobalFoundries and Apache Develop 28nm-SLP Sign-off Ready Flow

GlobalFoundries is jointly developing a 28nm-SLP sign-off ready flow with Apache Design Solutions using RedHawk™ and Totem™ to provide customers with a robust solution to meet their low power demands. The suite of Apache's products in the GlobalFoundries sign-off flow enables designers to perform early prototyping, circuit optimization, and full-chip sign-off.

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 Apache Hosts Technology Workshops at DATE

Chip-Package-System Methodology from Early Stage to Sign-off
Tuesday, 2011-03-15, 14:00 - 15:00

Workshop discusses the impact of power and noise on overall system cost and performance and how a proven CPS methodology, deployed early and throughout the flow to sign-off, addresses the power integrity and power induced noise challenges faced today. It will detail modeling, extraction and analysis technologies, and efficient model exchange capabilities required for bringing together SoC, IC package, and system designers to meet system cost and performance targets.

Click here to register

Power Methodology for Energy Efficient Designs
Wednesday, 2011-03-16, 12:30 - 13:30

Apache will demonstrate a power methodology highlighting the company’s broad portfolio of power and noise analysis platforms to address the needs of low power, energy efficient designs. It will include details of RTL power analysis, reduction and debug, custom IP validation and model creation, SoC integration, optimization and sign-off, to ensure power budgets are met while maintaining design integrity. It will also touch on advanced reliability challenges such as ESD and 3D IC, with respect to power, signal and thermal integrity.

Click here to register

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 DesignCon 2011 CPS Workshop Recap

Apache hosted the “Methodologies for Chip-Package-System Co-design with EMI/EMC Focus,” at DesignCon featuring presentations by leading experts on methodologies and technologies for CPS, EMI and EMC modeling and analysis. It included case studies and real design examples by speakers from LSI Corporation, Infineon Technologies, and the Missouri University of Science and Technology.

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© 2011 Apache Design Solutions, Inc. All rights reserved.

In This Issue

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  In the News

  Popular Whitepapers and Latest Blogs

  • Advanced Modeling Technologies for CPS Co-analysis/Co-optimization
  • RTL Design for Power Methodology
  • Power Noise Analysis for Next Generation ICs
  • PathFinder: Solution for Full-chip IC ESD Integrity
  • Power and Signal Line EM Design and Reliability Validation Challenges
  • Technologies for Power, Signal, Thermal, and EMI
  • Power and Noise Integrity for Analog/Mixed-Signal Designs

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