Oasys Design Systems Enhances Chip Synthesis With Power Capabilities

SANTA CLARA, CA -- (MARKET WIRE) -- Feb 24, 2011 -- Oasys Design Systems today unveiled the latest version of its revolutionary Chip Synthesis™ platform with enhanced capabilities that include chip-level power analysis and the ability to re-synthesize a design from the register transfer level (RTL) with new power constraints.

"Power is now the toughest design constraint," asserts Paul van Besouw, Oasys' president and chief executive officer (CEO). "Traditional synthesis tools can't handle power in ways that are effective for project teams because power is a chip-level problem not a block-level problem."

RealTime Designer™ allows power to be managed at the chip level and gives project teams a way to re-synthesize an existing RTL design to take into account a new power architecture. It can read input files from the Common Power Format (CPF) from Si2, the way low-power policies are described, and will soon support IEEE Standard 1801-2009, based on Accellera's Unified Power Format (UPF). It also supports multiple voltage threshold optimization and clock gating.

"CPF has enjoyed widespread industry adoption, with strong support from industry leaders and emerging companies such as Oasys Design Systems," says Steve Schulz, president and CEO of Si2. "I am confident their investment in CPF will continue to reap increasing dividends as the Low-Power Coalition advances CPF, for example the numerous powerful capabilities just released in CPF 2.0."

The tool offers a way for designers to experiment with voltage levels and power tradeoffs at the architectural level for maximum impact, while taking all power measurements from a fully placed netlist. During synthesis, RealTime Designer inserts all the appropriate level shifters, isolation cells and retention registers, as specified in the power policy.

It is not necessary to have a complete CPF or UPF file before using RealTime Designer. Instead, the power policy can be explored for various scenarios and RealTime Designer can be used interactively to consider alternative power policies without needing them to be fully specified in an external file. When this "what-if" analysis is complete and the final policy has been selected, RealTime Designer will write out the CPF or UPF file to be used by other tools, such as analysis and verification, and traditional place and route tools.

Chip Synthesis is a fundamental shift in how synthesis is applied to the design and implementation of integrated circuits (ICs). Traditional synthesis, with its limited capacity, forces power to be considered at the level of each individual block, and some master plan to be created to allocate the power budget among those blocks without really having any good information as guidance.

Block level tools do a poor job of handling chip-level issues. RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It features a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout.

RealTime Designer follows a "Place First" methodology that takes RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement it until chip-level constraints are met.

Availability and Pricing
The latest version RealTime Designer is shipping now and is priced from $395,000 (U.S.) for a one-year, time-based license.

About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates. It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide. Follow Oasys on Twitter at: www.twitter.com/OasysDS. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: Email Contact. For more information, visit: www.oasys-ds.com.

RealTime Designer and Chip Synthesis are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

For more information, contact:
Nanette Collins
Public Relations for Oasys Design Systems
(617) 437-1822

Email Contact 





Review Article Be the first to review this article

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
RELIABILITY ENGINEER... FRANCE for EDA Careers at FRANCE, France
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy