Accellera at DVCon: Learn About the UVM Standard

SAN JOSE, CA -- (MARKET WIRE) -- Feb 16, 2011 --

At its Design and Verification Conference and Exposition (DVCon), Accellera will offer a Universal Verification Methodology (UVM™) Workshop and its UVM experts will staff a booth during the event. In addition, a joint luncheon and Town Hall meeting with the Open SystemC Initiative (OSCI) will allow participants to exchange collaboration ideas.

The UVM Workshop will provide a comprehensive overview of the standard and educate verification engineers of all skill levels on the features of the first open-source methodology to be fully supported and endorsed by all the major EDA vendors and many end-user and consulting companies.
The Town Hall meeting and luncheon will bring together users of verification methods and tool developers and allow them to learn more and exchange ideas.

UVM Workshop
Monday, February 28, 9am-5pm

Monday, February 28, Noon-1:15pm

UVM Exhibit
Tuesday and Wednesday, March 1-2, 2pm-6:30pm, Booth #604

Doubletree Hotel San Jose, 2050 Gateway Place, San Jose, CA 95110

For more information about DVCon and to register, please visit
For more information about Accellera and its standards please visit

About Accellera
provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit For membership information, please email Email Contact.

UVM is a trademark of Accellera Organization, Inc. All other trademarks and tradenames are the property of their respective owners.

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