Jasper DVCon Highlights: ActiveProp and Advanced Formal Solutions

MOUNTAIN VIEW, CA -- (MARKET WIRE) -- Feb 07, 2011 --


WHAT: Jasper Design Automation's ActiveProp™ property synthesis tool will make its North American debut at this year's DVCon. ActiveProp automatically synthesizes properties to expand the property verification set, increase functional coverage, and identify coverage holes. Jasper is also highlighting its industry-leading formal solutions, including JasperGold®, ActiveDesign™ and Intelligent Proof Kits that speed the verification of SoC interconnect protocols. Jasper's advanced technology addresses verification challenges across the spectrum of design applications from architectural verification to post-silicon validation.

WHEN: DVCon will be held Feb. 28 - March 3. Exhibits are open Tuesday and Wednesday, March 1-2, 2pm-6:30pm.

WHERE: Jasper Booth #704, DoubleTree Hotel, San Jose, Calif.

About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 200 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.

Jasper Design Automation and the Jasper Design Automation logo are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.

Contact: 
Jim Lochmiller
lochpr
For Jasper Design Automation
(541) 292-0959

Email Contact 





Review Article Be the first to review this article
CST: Webinar October 19, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Upcoming Events
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise