GLOBALFOUNDRIES Unveils Industry’s First 28nm Signoff-Ready Digital Design Flows

Multiple 28nm design flows available through collaboration with leaders in EDA/IP ecosystem

MILPITAS, Calif. — (BUSINESS WIRE) — January 12, 2011 — GLOBALFOUNDRIES today introduced the industry’s first 28nm silicon-validated signoff-ready digital design flows to help chip designers deliver the next generation of power-sensitive mobile and consumer electronic devices. Developed in collaboration with EDA/IP ecosystem leaders and based on GLOBALFOUNDRIES’ 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG), the flows are precisely tuned to help overcome the unique challenges of designing and manufacturing integrated circuits at leading edge nodes.

The new signoff-ready flows were developed with recognition of the need for silicon validation to ensure first-time-right silicon success, setting a new standard for quality, scope, and relevance in foundry flows. Customers can now produce signoff ready 28nm designs using the industry’s most advanced set of synthesis, place and route, sign-off, and DFM tools, tool scripts, and methodologies.

“Many of the world’s top IC designers are using our 28nm technology to deliver tomorrow’s most innovative mobile and consumer devices,” said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. “By collaborating closely with our partners in the EDA/IP ecosystem to provide a comprehensive 28nm design platform, we are giving customers confidence that their designs will be brought to life smoothly and in time to meet their critical market requirements.”

Traditional foundry design flows have not taken into account the growing interaction of design and manufacturing at advanced technology nodes. GLOBALFOUNDRIES has addressed these issues by emphasizing early collaborative development with providers of EDA software and IP to validate design methodologies against real silicon. In addition to tight integration with GLOBALFOUNDRIES’ signoff physical verification solution, all flows leverage GLOBALFOUNDRIES’ heritage as a leader in Design-for-Manufacturing (DFM) by supporting DRC+, the company’s silicon-validated solution that goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable up to a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.

GLOBALFOUNDRIES and Cadence have jointly developed a complex 28nm-SLP design that fully demonstrates Cadence’s portfolio of advanced silicon implementation tools, including high-level synthesis, low power, routing, DFM, and verification. The 9 mm2 multi-million gate design is architected to highlight and showcase advanced 28nm chip implementation techniques and to enable quantitative silicon validation of power, performance, and area tradeoffs, as well as robustness and yield. The design is being released to manufacturing and is expected to be silicon validated in the first half of 2011. The full design, implementation scripts, and a set of recommended methodology white papers on 28nm routing and DFM will be available to customers starting in Q1 of 2011.

GLOBALFOUNDRIES and Synopsys have collaborated to develop a 28nm-SLP design flow based on the Synopsys Galaxy™ Implementation Platform, together with a 28nm-SLP Foundry-Ready System technology plug-in for the Lynx Design System. The silicon-proven design flow integrates the GLOBALFOUNDRIES 28nm-SLP design rules with Synopsys’ latest EDA technologies, including PrimeTime® advanced on-chip variation analysis, IC Compiler’s DFM-optimized Zroute router and In-Design physical verification, and IC Validator DRC and DRC+ pattern support. The Lynx Foundry-Ready System adapts Lynx’s Galaxy Platform-enabled production design flow to GLOBALFOUNDRIES’ technology and includes guidelines and tool settings based on the latest 28nm silicon data to help ensure the highest quality and the most robust designs. The Lynx Foundry-Ready System addresses recommended routing rules, on-chip-variation and advanced on-chip variation analysis, and DFM, enabling a more efficient handoff with the foundry. Both the foundry design flow and 28nm-SLP Lynx Foundry-Ready System are expected to be available to customers starting in Q1 of 2011.

GLOBALFOUNDRIES and Mentor Graphics are developing a complete reference flow based on the Olympus-SoC™ and Calibre® InRoute™ products. The Olympus-SoC router has been qualified for GLOBALFOUNDRIES’ 28nm-SLP technology, providing support for both advanced 28nm ground rules and recommended rules to implement DFM, improved recipes for efficient routing, and support for manufacturing scoring analysis (MAS).

GLOBALFOUNDRIES and Magma have worked to develop a 28nm-SLP signoff-ready flow based on the Talus® Vortex IC implementation platform. Talus Vortex is an ideal physical design environment for engineers creating complex systems on a chip (SoCs) at all process nodes and where performance and power management are crucial. It dramatically improves productivity by allowing designers to implement up to 1.5 million cells or more per day on large designs or blocks – with crosstalk avoidance, advanced on-chip variation (AOCV) and multi-mode multi-corner analysis enabled. Talus also performs advanced low-power design analysis and optimization via an automated multi-Vdd methodology. Talus has already been used by Magma’s and GLOBALFOUNDRIES’ mutual customers to meet aggressive time, power and performance targets.

GLOBALFOUNDRIES is jointly developing a 28nm-SLP signoff-ready flow with Apache Design Solutions using RedHawk™ and Totem™ to provide customers with a robust solution to meet their low power demands. RedHawk is a production proven power signoff platform for large scale SoCs including those with ultra-low power design techniques. Totem offers power, noise, and reliability sign-off for analog/mixed-signal designs. The suite of Apache’s products in the GLOBALFOUNDRIES’ sign-off flow enables designers to perform early prototyping, circuit optimization, and full-chip sign-off.

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