Jasper Formal Technology Newsletter Q4 2010

Formal Technology Newsletter
Q4 2010

As we look forward to the end of the decade (how time flies!) and the holiday season, I want to personally thank all of you who have made this past year such a successful one for Jasper. We are honored to work alongside so many wonderful, innovative and creative people whose products are truly shaping a whole new world.

Happy Holidays! And Best Wishes for a Joyous and Prosperous New Year,

Kathryn Kranen, CEO

Jasper Corporate News
Lucio Lanza Joins Jasper Design Automation Board
Brazil: A High-tech Hot Spot for Innovation and Investment
What Can be Expected From the Accellera Unified Coverage Interoperability Standard?
Jasper Technology News
Using Formal Verification To Control X Propagation

Jasper formal verification provides the most realistic treatment for unknowns.

Featured Visualize Technology

Visualize allows designers and verification engineers to explore what-if scenarios without a testbench.

More technology feature videos are available at

JasperGold and ActiveDesign Video Demos

Flagship JasperGold™ unleashes formal verification on top project challenges spanning the IC development cycle.

ActiveDesign™ accelerates design creation and IP leverage with system and databases for RTL analysis, RTL design development, quality and reuse.

Jasper's Unique Features Accelerate Formal Verification Deployment

Jasper's award-winning ActiveDesign brings the power of formal to RTL development, letting you easily design and verify RTL that's then stored in a database... to simplify IP reuse and downstream verification.

Formal Verification Solves Asynchronous Design Challenges

As design complexity has increased significantly over the years, verification of asynchronous designs has become one of the biggest challenges in modern SoCs. Functional simulation, linting and other traditional verification methods have proved to be inadequate in accurately and exhaustively verifying asynchronous designs.

Think Parallel First, Then Cloud for EDA

Jasper formal verification leverages parallel computing.

Protect Your Goal With Post-silicon Formal Verification

SoC designers are learning the benefits of applying Jasper formal tools all the way through post-silicon debug.

Jasper Customer News
Jasper Users Group Meeting   November 2010

Summary of the seventh annual Jasper Users Group Meeting.

Applications Spectrum and Customer Videos

3 customers, 8 applications engineers, and Jasper CEO comment on what makes Jasper great!

21 Proof Points for Formal in Computing, Mobile and Graphics

Jasper solves real-world problems in computer, mobile and graphics designs across 7 applications.

Highlights of DAC 2010 Customer Presentations

IP-SOC   Nov 30 - Dec 1, 2010
Grenoble, France

Jasper CEO Kathryn Kranen will present "Post-Silicon Debug: A New Approach for Solving the Unspoken and the Urgent".

IEEE Microprocessor Test & Verification Workshop   Dec 14, 2010
Austin, TX

Jasper CTO Dr. Rajeev Ranjan Ranjan in a special session covering formal methods for power and performance verification.

DesignCon   Jan 31 - Feb 3, 2011
Santa Clara Convention Center, Santa Clara, California

Jasper will present "Automating higher level verification methods".

EDSFair   Jan 27 - Jan 28, 2011
Pacifico Yokohama, Japan

Visit the Cybertec / Jasper booth and see the Jasper presentation.

DVCon   Feb 28 - Mar 3, 2011
Double Tree Hotel, San Jose, CA

Visit Jasper at booth 704!

To meet with the design and verification deployment experts at Jasper at any of the above events, or for more information on Jasper Design solutions, please send email to info@jasper-da.com or call 1.650.966.0266.


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