MONROVIA, California – November 10, 2010 – With pressure to reduce time to market and with resources increasingly constrained, tools that can enable maximum productivity are mission-critical. Tanner EDA’s L-Edit physical layout for physical layout is a powerful, robust layout editor that nearly 10,000 design teams have used to create breakthrough analog integrated circuits (ICs), with virtually no learning curve to get started.
Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal ICs, is holding two free webinars in November on how to use L-Edit to reduce the unpredictable costs and workload related to a tapeout deadline. Webinars also will touch on further increases in efficiency made possible by using L-Edit integrated with Tanner EDA’s tool for layout acceleration – HiPer DevGen.
- Register Now Nov 19, 2010 - 9:00 AM PST - L-Edit Webinar
- Register Now Nov 30, 2010 - 2:00 PM PST - L-Edit Webinar
For a 30-day free trial of Tanner tools to see for yourself the benefits of L-Edit or HiPer DevGen, click here
Or click here to download the L-Edit datasheet
About Tanner EDA
Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.
Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.
HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc.
All other trademarks and trade names are the property of their respective owners.