Averant Announces Toshiba Expanding Deployment of Solidify

HAYWARD, Calif. & TOKYO — (BUSINESS WIRE) — November 4, 2010 — Averant Inc., a leading provider of advanced verification technologies for digital designs, today announces that Toshiba Corporation has expanded deployment of Averant’s formal verification tool Solidify.

Toshiba and Averant have been collaborating on Solidify usage in verification flows for several years. Starting in 2003, Solidify was selected to be a recommended tool in the verification platform and its autocheck feature was routinely applied on SoC designs under development. Recently, as SVA (System Verilog Assertion) property development usage has increased and new verification features such as Sequential Equivalency Checking to check design retiming are being introduced, Toshiba decided to expand the number of Solidify licenses. The advantages of adopting Solidify’s property checking for Toshiba designs are numerous, including identifying issues not detected by simulation and ensuring circuit correctness after those issues have been fixed. By using Solidify in the verification flow, high quality SoC designs verification can be achieved.

“Delivering bug-free quality designs to the market quickly is a priority for our organization,” said Takashi Yoshimori, Assistant to Chief Technology Executive of Toshiba Corporation Semiconductor Company. “While design sizes increase and development cycle times decrease, delivering well-verified high-quality design becomes ever more difficult. Solidify formal verification techniques and high performance engines help us meet the challenge of verifying the next generation circuits efficiently.”

Averant’s flagship product Solidify is a complete formal verification tool which supports standard design and property languages: Verilog, VHDL, SVA, PSL. It includes automatic checks for common design errors such as deadlock or deadcode, and static coverage analysis to help develop a complete property suite. Advanced features such as testbench-less bug hunting, sequential equivalency checking and guided proof system further maximize the return of investment on formal technology.

“I am delighted to see Toshiba’s continued approval of our products,” said Ramin Hojati, Averant’s President. “Toshiba is an outstanding organization, which has continuously provided valuable feedback and product direction to us over the past decade. These comments have significantly influenced the development of many features including auto checks, more powerful engines, language support and sequential equivalency checking.”

About Averant

Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s flagship product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. Averant’s tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.


Averant, Inc.
Ramin Hojati, 510-205-9815
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