Verific Joins Cadence Connections Program

Move Enables Access to Software, Support to Develop Validated Interfaces

ALAMEDA, CALIF. –– October 20, 2010 –– Verific Design Automation, supplier of de facto standard SystemVerilog and VHDL front-end software to the electronic design automation (EDA) and semiconductor community, announced today that it has become a member of the Cadence Design Systems Connections® program. 

Cadence® Connections is a program that enables interoperability between EDA software.  As a member of this program, Verific has access to Cadence software and support to ensure SystemVerilog and VHDL interoperability between Cadence products and the EDA tools that incorporate Verific’s front ends.

“Teaming with innovative technology companies such as Verific is a key to Cadence delivering on the promise of the EDA360 vision,” said Tom Anderson, product marketing group director at Cadence.  “We’re pleased to welcome Verific to Connections and look forward to working with them on common interpretation of standard languages.”

Verific will calibrate its software, the front end to a variety of Field Programmable Gate Array (FPGA) and EDA tools for synthesis, simulation, debug, test and verification applications, to the Cadence tool flow.  Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux, and Windows operating systems.  Licenses come with support and maintenance.

“Joining the Connections Program is a strategic move for us,” added Michiel Ligthart, Verific’s chief operating officer.  “Interoperability between our SystemVerilog and VHDL front ends and Cadence’s tool flow will offer design teams an unobstructed path to implementation and, most important, more accurate designs.”

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard SystemVerilog, Verilog and VHDL front-end software.  Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies.  Corporate headquarters is located at:  1516 Oak Street, Suite 115, Alameda, Calif.  94501.  Telephone:  (510) 522-1555.  Facsimile number:  (510) 522-1553.  Email:  Email Contact.  Website:  www.verific.com.

###

 

For more information, contact:

Nanette Collins                                    

Public Relations for Verific                   

(617) 437-1822

Email Contact

 

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. 




Review Article Be the first to review this article
Aldec

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Director, Business Development for Kongsberg Geospatial at remote from home, Any State in the USA
Director, Business Development for Kongsberg Geospatial at Ottawa, Canada
Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL
DAC2018



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise