CAMPBELL, Calif. — (BUSINESS WIRE) — October 11, 2010 — Altos Design Automation Inc. today announced that MoSys, Inc. (Santa Clara, CA) has adopted Liberate, its ultra-fast cell characterization solution. MoSys is using Liberate to re-characterize foundry-based standard cell libraries and for characterization of its internally designed high speed interface (I/O) cells.
“We are using Liberate to fully re-characterize the TSMC 65 nm cell library and to create consistent library views for our internally designed IP,” stated Samir Mitra, Vice President of Corporate Development for MoSys. “We are pleased with the performance and ease-of-use we’ve experienced with Liberate, especially in automatically modeling our complex, high-speed I/Os.”
Jim McCanny, Altos CEO and founder, said, “Essential to an IP provider is the ability to create industrial strength library models efficiently as possible.” McCanny continued, “Using Liberate, MoSys can utilize the same modeling approach as its foundry partner and enjoy the best characterization performance and accuracy in the industry. Our latest 3.0 product release further improved upon Liberate’s ability to automate complex I/O characterization and to create accurate IBIS models that can be used for off-chip signal integrity analysis by package and board simulators.”
Liberate is an ultra-fast library creator that generates electrical models in Liberty®, Verilog, Vital and IBIS formats. Liberate supports all the latest models for timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective Current Source Models) Liberate also supports ultra low power and high speed design styles that include power gating cells, state retention registers, level shifters, pulse clocking and CML.
About MoSys, Inc.
MoSys, Inc. is a leading provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs. MoSys' Bandwidth Engine™ family of ICs combines the company's patented 1T-SRAM® high-density memory technology with its high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology. A key element of Bandwidth Engine technology is the GigaChip™ Interface, an open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications. MoSys' IP portfolio includes SerDes IP and DDR3 PHYs that support data rates from 1 - 11 Gbps across a variety of standards. In addition, MoSys offers its flagship, patented 1T-SRAM and 1T-Flash® memory cores, which provide a combination of high-density, low power consumption, high-speed and low cost advantages for high-performance networking, computing, storage and consumer/graphics applications. MoSys IP is production-proven and has shipped in more than 325 million devices. MoSys is headquartered in Santa Clara, California. More information is available on MoSys' website at http://www.mosys.com. MoSys, 1T-SRAM and 1T-Flash are registered trademarks of MoSys, Inc. The MoSys logo, Bandwidth Engine and GigaChip are trademarks of MoSys, Inc. All other marks mentioned herein are the intellectual property of their respective owners.
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 1919 South Bascom Ave., Suite 250, Campbell, CA 95008. Telephone: (408) 980-8056. On the Web at: http://www.altos-da.com